Required timing model (.v) for LPPDR4 simulation using Hyperlynx

キャンセル
次の結果を表示 
表示  限定  | 次の代わりに検索 
もしかして: 

Required timing model (.v) for LPPDR4 simulation using Hyperlynx

1,399件の閲覧回数
aprakashbaler
Contributor I

I am simulating for SI in hyperlinx for LPDDR4 interface at 4000mbits/s. there are failuers in max slew rate for all the drive strength and ODT configurations for Data write cycle. 

Required timing model or any solution to reduce the slew rate. 

Regards

Avinash B P

タグ(3)
0 件の賞賛
返信
3 返答(返信)

1,366件の閲覧回数
AldoG
NXP TechSupport
NXP TechSupport

Hello,

Could you share the device that you are testing?
Also, which verion of the IBIS file you are using?

Best regards/Saludos,
Aldo.

0 件の賞賛
返信

1,344件の閲覧回数
aprakashbaler
Contributor I

Hello Aldo,

 

Device i am using is MIMX8ML8CVNKZAB.

and the IBIS used is ibis_imx8mp_v2_20201023.

Regards

Avinash B P

0 件の賞賛
返信

1,244件の閲覧回数
AldoG
NXP TechSupport
NXP TechSupport

Hello,

max slew rate failures are not seen as a high risk. We recommend for customers follow our Hardware Developer's Guide and good design practices. And that should be enough.

Best regards/Saludos,
Aldo.

0 件の賞賛
返信