In IMX8M Mini We want to use NAND FLASH INTERFACE for booting and 3xUSDHC interface for module functionality. But as per IMX8M Mini Datasheet in table 63 same IO's are been used for both NAND FLASH & USDHC IP. So on successful booting of processor can the NAND_xxx pads can be configured for accessing it as USDHC-3 IP. Please clarify. if any design examples are available please share.
