Hi Paul,
Take care VSNVS voltage got a maximum rating of 3.3V, even 3.15V nominal would require below 10% precision.
If they want to connect those pullup to a different voltage than VSNVS, this is a violation of power supply group, depending on voltage sequence (like in modes where only VNSVS is present), you can power part of the chip through that I/O and not something to advice in any case.
This might not be the same as what you describe as leakage but the problem we had on this rail with first generation of PFuze PMIC was the limitation of current to 200 and 400 uA (this is being increased on latest revision) meaning you really had to count every resistor on that rails : POR_B got internal pull up, no need to add external, on BOOT_MODEx pins could be as high as 100 K (got confirmation from analog team) unless you want to boot from fuses. Check also TAMPER, TEST_MODE, ONOFF, and PMIC_STBY, PMIC_ON also on that rail.
Cheers, Philippe.