Hi,
Please let me make clear about below questions.
1) Each SSIx(x=1,2,3) is included STCK/STFS/SRCK/SRFS/STXD/SRXD signal lines?
2) Each SSIx(x=1,2,3) are connected to internal port 1/2/7 of AUDMUX. Is this understanding correct?
3) we can set port to port connection inside AUDMUX?(default configuration is below figure)
Best regards,
yuji
Dear Igor,
Please let me ask an additional question about relationship of signal name for each module; SSI, AUDMUX and IOMUX.
Below relationship about signal name is correct?
[SSI] [AUDMUX(x=3,4,5,6)] [IOMUX(x=3,4,5,6)]
1.STCK <---------> TxCLKx <---------> AUDx_TXC
2.STFS <---------> TxFSx <---------> AUDx_TXFS
3.STXD <---------> TxDx <---------> AUDx_TXD
4.SRCK <---------> RxCLKx <---------> AUDx_RXC
(network clk)
5.SRFS <---------> RxFSx <---------> AUDx_RXFS
6.SRXD <---------> RxDx <---------> AUDx_RXD
Br,
Yuji
Hi Yuji
interconnections are described in AN2628
https://www.nxp.com/docs/en/application-note/AN2628.pdf
Best regards
igor
Hi, Igor
thanks for you explanation.
I understood.
Br,
yuji
Hi Yuji
1. yes
2. this depends on used processor, for example for i.MX6Q it is described in
Table 81. AUDMUX Port Allocation
i.MX 6Dual/6Quad Applications Processors for Consumer Products - Data Sheet
3. right
Best regards
igor
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