Reference design for i.MX6 and 32bit DDR3

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Reference design for i.MX6 and 32bit DDR3

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vladislavkasik
Contributor II

Hi,

Does Freescale have a reference design for i.MX6 and DDR3 memories connected in 32 bit configuration, preferably with 0402 blocking caps as the smallest part?

We would like to start with i.MX6 Solo and if we need more power we could migrate to Dual or Quad.

Thank you very much,

Vladislav

jiri-b36968

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YixingKong
Senior Contributor IV

Vladislav

This discussion is closed since no activity. If you still need help, please feel free to reply with an update to this discussion, or create another discussion.

Thanks,

Yixing

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YixingKong
Senior Contributor IV

Vladislav

Had your issue got resolved? If yes, we are going to close the discussion in 3 days. If you still need help, please feel free to reply with an update to this discussion.

Thanks,

Yixing

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jiri-b36968
NXP Employee
NXP Employee

Hi Vladislav,

yes Freescale does support DDR3 reference design. It is done on SDB board. Nevertheless this design is 64bit DDR3 only. We do not have 32 bit reference design for DDR3. There is possibility to use 32bit DDR3 design on validation board, but this is not optimized.

What we support is 32bits LP-DDR2 reference design on SL. SL is for lowest power same like LP-DDR2.

So please consider to use

  • i.MX6SL + 32bits LP-DDR2
  • or i.MX6DL,i.MX6D or i.MX6Q with 64bits DDR3.

Reference design is using 0402 capacitors, since it is smallest size accepted by Automotive.

/Jiri

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marcocavallini
Contributor V

Hello,

I am working on a board mounting i.MXSOLO and 32bit DDR3 (2x MT41K128M16) and a total of 512MB

Is this design supported by the CPU?

What do you mean with "There is possibility to use 32bit DDR3 design on validation board, but this is not optimized"?


Thank you

--

Marco

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jiri-b36968
NXP Employee
NXP Employee

Hello Marco,

Yes i.MX6S + 32bit DDR3 is valid combination.

I meant that reference design which is simulated, implemented, tuned and documented is done as 64bit for DL/D/Q. This design can be copied to avoid any issues with DDR.

Unfortunately there is no reference design for i.MX6S + 32bit DDR3. Closest is i.MX6SL + LPDDR2.

/Jiri

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mahi
Contributor IV

Hi Jiri,

you wrote "Reference design is using 0402 capacitors, since it is smallest size accepted by Automotive".

Where can I find this reference design? For which i.mx6-Device is this design?

Best Regards

Martin

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jiri-b36968
NXP Employee
NXP Employee

Hi Martin,

it is available at Freescale web pages.

There are two reference designs:

  • SDB Board (SDP platform)
  • AI automotive infotainment

all at:

http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=i.MX6Q&fpsp=1&tab=Design_Tools_Tab

Printed Circuit Boards and Schematics-Schematics section

/Jiri

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mahi
Contributor IV

Hi Jiri,

you mean the SABRESD and SABREAI Platforms?

Both are using 0201 capacitors for decoupling the supply of i.MX6.

The decoupling of the memories is 0402, but my hope was there would be a reference design without 0201 at all.

Best Regards,

Martin

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jiri-b36968
NXP Employee
NXP Employee

Hi Martin,

there are no other reference designs. 0201 is used for maximal efficiency of bypassing capacitors - correct placement. Sorry for misunderstanding. I mean that it is sometime problem to use 0201 design because of rules in Automotive industry. It is hard or not possible to do same layout with 0402 to get correct bypassing.

/Jiri

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