Reducing ECSPI CS High Time Without Using DMA

[mehul_dabhi]

Hi there,

I am facing an issue where the Chip Select (CS) remains high for approximately 5 µs.

Initially, while using DMA, I observed an extended CS low time of around 2.2 µs before the SCLK (Serial Clock) starts. I received a suggestion to use native CS with DMA disabled.

[Here is the link  to the entire discussion.]

Now, I have disabled DMA and am using native CS for the SPI peripheral, but I still observe that CS remains high for approximately 5 µs.

Even when I increase the SPI clock speed, the idle time of CS remains almost unchanged, while the low time (transaction time) improves.

Can you please tell what's causing this issue? And any steps to resolve it? 

Any help / suggestions would be appreciated

Thanks,
Mehul

[mehul_dabhi]

Please find below an inline answer. 

Is your 2.2 us / 5 us at the beginning of the SPI burst, or are you seeing those between byte transmissions?

Ans. in between byte transfers, we have observed this delay 

What is the SCLK that SPI is working with?
Ans. 30 MHz

How to eliminate this delay to increase spi sampling due to this delay, it is adding ~5 us delay in every transaction. We are not able to achieve the SPI-required speed.

[JosephAtNXP]

Hi,

Thank you for your interest in NXP Semiconductor products,

Is your 2.2 us / 5 us at the beginning of the SPI burst or are you seeing those between byte transmissions?

What is the SCLK that SPI is working with?

Seems like it's a natural delay since the time is really short, but we will confirm it.

Regards

[mehul_dabhi]

Hi @JosephAtNXP ,

The issue was related to the burst transfer initialisation, not in the byte transfer.
And for your reference, I am attaching the snap of the 2us delay too.

The Blue one is SCLK signal
and the yellow one is CS signal.

Let me know if you require anything to recreate the issue and to debug it further.