Dear Community,
I have a question about the i.MX6UL.
Question
１．Please tell me how many 〇us after VDD_SNVS_CAP (1.1V) is output after VDD_SNVS_IN (3.3V) is input.
２．Do Limitations 1 and 2 below not need to be considered in a transient state?
(When an external 1.0V voltage is input to XTALI at the same time as VDD_SNVS_IN)
Conditions
１．VDD_HIGH_IN and VDD_SNVS_IN are shorted, and this 3.3V power source has a margin of current that can be passed.
２． No load is connected to VDD_SNVS_CAP.
３．No button battery
４．BOOT MODE [1:0] = 1:0 (internal boot) using QSPI
Background
We input an external 32kHz clock to XTALI (T16).
However, there are three limitations listed in the Hardware Development Guide (HDL):
Limitation
１．HDG_P13 RTC_XTALI should not exceed the voltage value of VDD_SNVS_CAP (approximately 1.1V).
２．HDG_P13 The RTC_XTALI signal should not be driven if the VDD_SNVS_CAP supply is off.
３．HDG_P11 Do not connect any loads to VDD_SNVS_CAP.
Solution
１．Set the upper voltage limit of the clock signal to an external power supply of 1.1V or less.
２．External power supplies less than 1.1V should be started after VDD_SNVS_CAP.
３．No load is connected to VDD_SNVS_CAP.
Best Regards.
