Hello,
In the datasheet for i.MX8MQ section 3.2.1 Power-up sequence, the following requirements is specified in step 3:
• RTC_RESET_B release (after 32K clock stable and before POR_B release, no constraint with any
other power supplies)
My questions are as follows:
1) What does "after 32K clock stable and before POR_B release, no constraint with any
other power supplies" mean? Does it say that the signal should be released after a certain number of clock cycles? POR_B release is the last step in the sequence, so it makes sense that RTC_RESET_B must be released before that. How about the last part - "no constraint with any other power supplies.
2) What controls RTC_RESET_B release timing to ensure that it is released after Step 2 (Turn on VDD_SNVS) and Step 4 (Turn on VDD_SOC and VDDA_0P9)?
Thank you
Solved! Go to Solution.
@mmovsisyan
Hello,
32K clock stable means, that the clock signal voltage is proper, frequency
is in allowed range. RTC_RESET_B release can occur in any time between
turning on of both NVCC_SNVS, VDD_SNVS and POR_B release.
Regards,
Yuri.
@mmovsisyan
Hello,
32K clock stable means, that the clock signal voltage is proper, frequency
is in allowed range. RTC_RESET_B release can occur in any time between
turning on of both NVCC_SNVS, VDD_SNVS and POR_B release.
Regards,
Yuri.