RT1172 MIPI DSI_COMPLIANT_TEST MIPI CLOCK issue

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RT1172 MIPI DSI_COMPLIANT_TEST MIPI CLOCK issue

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496387703
Contributor I

hi all:

when i use the demo from mdk——mipi_dsi_compliant_test_cm7

when set:

const clock_root_config_t lcdifClockConfig = {

    .clockoff = flase,

    .mux = 4, // PLL_528

    .div = 8,

}

CLOCK_SetRootClock(kCLOCK_Root_lcdifv2, &lcdifClockConfig);

mipiDsiDpiClkFreq_Hz = CLOCK_GetRootClockFreq(kCLOCK_Root_lcdifv2);

at this set, the mipiDsiDpiClkFreq_Hz = 66,000,000, mipiDsiDpyhBitClkFreq_Hz = 888,000,000

 

if I change the .div,  When .div = 3, the mipiDsiDpiClkFreq_Hz = 176,000,000, But, mipiDsiDpyhBitClkFreq_Hz = 0. so, What is the maximum value of mipiDsiDpiClkFreq_Hz??if I want mipiDsiDpiClkFreq_Hz = 200,000,000. How to set up the clock?

Good wishes!

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EdwinHz
NXP TechSupport
NXP TechSupport

Hi @496387703,

LCDIF clock root cannot be greater than 150MHz. Here I am using Clocks from Config Tools. As you can see, when the divider is /4, the root out frequency for this module is the expected 132MHz and there is no issue:

EdwinHz_1-1701729799975.png

However as when I set the divider to /3, as you do, I indeed get an output frequency of 176MHz as you mention. However, ConfigTools also shows an error message, stating that the output frequency must be lower than or equal to 150MHz:

EdwinHz_0-1701729688255.png

Let me know if this answers your question.

BR,
Edwin.

 

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496387703
Contributor I

thank!

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