Update
I found an NXP application note on the i.MX RT FlexRAM. It explains out most of my questions. I figured out how to adjust the memory sizes in code using the porvided information.
https://www.nxp.com/docs/en/application-note/AN12077.pdf
The application note, it states:
“The most critical code to execute as fast as possible (without the wait states to fully utilize the super-scalar pipeline nature of Cortex-M7) must be placed into the ITCM (Harvard bus architecture nature is preferred in this consideration). The less important data (accessed sporadically) should be placed in the external memory. The data that is accessible only by the core (stack, static data, and so on) must be placed into the DTCM. The Cortex-M7 core also supports direct access to the TCM through the AHBS interface. The DMA master can still access the TCM through the AHBS. However, the access is not as fast as the access by the core. It shall be used when the core is sleeping/powered down.
The data accessed by more than one bus master (for example; the core and DMA) should be placed in the OCRAM, especially when it is accessed by the DMA in the low-power modes.”
I will be storing and executing my main code from SDRAM, I also am using the Keil RTX RTOS and network application. How do I decide which code should go where?
