RT1050-EVK Board FlexRAM Memory Settings Help

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RT1050-EVK Board FlexRAM Memory Settings Help

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kamal1
Contributor II

Hello,

 

 

 

I am working with the MIMXRT1050-EVKB demo board. I want to place code in internal ram for execution and have some questions about the FlexRAM memory settings. In the manual, I found that this boards equipped with 512KB of on-chip RAM, which is shared by ITCM, DTCM, and OCRAM. I tried to read back the FlexRAM register to see the current layout of the 512KB, but I did not get anything back. It appears to be controlled by the internal fuses. Then I tried to read back the fuse state, but I then get this fuse address is read locked. Here are my questions:

 

 

 

  1. What is the purpose of having ITCM, DTCM, and OCRAM when they all use the same 512KB? Why not just make it one region like all 512KB of OCRAM?

 

 

 

  1. How can I confirm the current use of the 512KB using the FlexRAM register or fuse settings?

 

 

 

  1. How can I change the FlexRAM memory layout to add or use less memory for a specific region? Does this have to be done through the fuses or can it be done through the board.c BOARD_ConfigMPU function?

 

 

 

Thanks,

 

Kamal

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kamal1
Contributor II

Update

 

I found an NXP application note on the i.MX RT FlexRAM. It explains out most of my questions. I figured out how to adjust the memory sizes in code using the porvided information. 

https://www.nxp.com/docs/en/application-note/AN12077.pdf

 

 

The application note, it states: 

 

“The most critical code to execute as fast as possible (without the wait states to fully utilize the super-scalar pipeline nature of Cortex-M7) must be placed into the ITCM (Harvard bus architecture nature is preferred in this consideration). The less important data (accessed sporadically) should be placed in the external memory. The data that is accessible only by the core (stack, static data, and so on) must be placed into the DTCM. The Cortex-M7 core also supports direct access to the TCM through the AHBS interface. The DMA master can still access the TCM through the AHBS. However, the access is not as fast as the access by the core. It shall be used when the core is sleeping/powered down.

The data accessed by more than one bus master (for example; the core and DMA) should be placed in the OCRAM, especially when it is accessed by the DMA in the low-power modes.”

 

 

 

I will be storing and executing my main code from SDRAM, I also am using the Keil RTX RTOS and network application. How do I decide which code should go where?

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victorjimenez
NXP TechSupport
NXP TechSupport

Hi Kamal, 

The best performance is achieved by placing the instructions in ITCM and the data in DTCM. Please refer to the following community thread: Choosing between ITCM and DTCM on IMXRT

Regards, 

Victor 

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