RPMsg Shared Memory Communication Between M33 and A35 on i.MX8ULP (90KB SPI Data Transfer)

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RPMsg Shared Memory Communication Between M33 and A35 on i.MX8ULP (90KB SPI Data Transfer)

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Dhaval_Shiroya
Contributor I

Hello everyone, 

I'm working on a custom board based on the i.MX8ULP and need to set up communication between the Cortex-M33 core and the Cortex-A35 core using RPMsg and shared memory

On the M33 side, I have an SPI-connected peripheral that sends 90 KB of data

Here's the flow I want to implement: 

  1. The A35 core (running Linux) sends a "START" command to the M33 core using the imx_rpmsg_tty driver. 
  2. In M33, I have implemented all the logic into separate task parallel to RPMSG task into rpmsg_lite_str_echo_rtos example. 
  3. When M33 receives this command, it starts collecting 90 KB of data from the SPI peripheral. 
  4. The M33 then stores this data into specific address of shared memory buffer
  5. The A35 core should be able to read this data from shared memory

My Questions:

  1. How can I allocate and store the 90 KB of data into a fixed shared memory location on the M33 side? 
  2. How should I reserve and access this shared memory from the A35/Linux side?
  3. How can I make sure the memory is non-cacheable on both cores, so there are no data inconsistency issues? 
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Manuel_Salas
NXP TechSupport
NXP TechSupport

Hello @Dhaval_Shiroya 

I hope you are doing very well.

 

Please, take a look to the sai_low_power_audio example of i.MX8ULP SDK.

 

In this demo, A core decoded music data and put it to DDR buffer and informs M core with the related information. Then M core will take the ownership of consuming the buffer, it will copy buffer from DDR to TCM, manipulating SDMA to transfer the data to SAI and codec for playback.

 

You can take as reference to the imx8ulp-evk-lpa.dts device tree.

 

Best regards,

Salas.

 

 

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