No, I really mean "SPI NAND flash" (not SPI NOR, not parallel NAND), so something which is not directly bootable by the imx6SL ROM.
That's why the first stage will be a 4KB bootloader on eeprom, knowning just enough of the bad blocks & bad bits to look for multiple copies of uboot inside this Nand.
Since I want to keep the uboot header (IVT+ DCD...) as similar as the original, it must manage DCD process and/or plugins inside this first stage, or at least, forward the process to the ROM code (through a possible ROM API)
I don't want to put the DCD part inside this 4KB, since:
- 4KB is already very small
- if possible, I don't want to update this first stage when the DDR parameters will need to change (experience shows It can be frequent...)
Regards,
Arnaud