RMII on iMX6 SoloX

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RMII on iMX6 SoloX

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mchaplet
Contributor II

Hi,

I previously used RMII on a iMX6 Solo/DualLite with "GPIO16 ref clock loopback" feature. (Generating 50MHz from iMX for internal reference AND external Phy)

It seems that this feature is quite different on SoloX and there is no explanation in Hardware Guide (Contrary to IMX6S/IMX6DL)

There is a 25MHz reference clock "ref_enetpll2" quite simple to configure and output through Pad Muxing.

But I don't see other references (50/100/125).

My Goal is to generate a 125MHz on signal ENET1_REF_CLK (output through pad ENET1_TX_CLK)

and a 50MHz on ENET2_REF_CLK (output through pad ENET2_TX_CLK)

I'm working on U-Boot 2015.07 and I already tried to activate 125MHz as done by mx6sxsabresd initialization without success.

I've tried also to implement it myself on ENET2 by :

* Setting ENET2_TX_CLK_DIR and ENET2_CLK_SEL bits to 0 in IOMUXC_GPR_GPR1 register

* Setting right Divider and starting PLL (reg CCM_ANALOG_PLL_ENET)

* Waiting for Lock -> Lock OK

* Disabling Bypass and enabling output (BM_ANADIG_PLL_ENET2_ENABLE = 1 and BM_ANADIG_PLL_ENET_BYPASS = 0)

All seems right but nothing on output.

Is it missing a PAD configuration ? (Like SION Mode in IMX6DL case)

What seems strange to me is that 25MHz is really easy to output through ENETx_RX_CLK muxing and is well working.

Why other "Enetpll" outputs are so difficult to configure in out ?

Thanks for any help,

Martin

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Martin

I think one can reuse code from attached uboot mx6sxsabresd.c

if (0 == fec_id)
/* Use 125M anatop loopback REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/
clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0);

changing gpr1[17] to 1:

1 ENET1_TX_CLK output driver is enabled when configured for ALT1

also recommended to set pad settings for 125MHz output as:

SPEED=11, DSE=111

Best regards

igor

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Martin

I think one can reuse code from attached uboot mx6sxsabresd.c

if (0 == fec_id)
/* Use 125M anatop loopback REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/
clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0);

changing gpr1[17] to 1:

1 ENET1_TX_CLK output driver is enabled when configured for ALT1

also recommended to set pad settings for 125MHz output as:

SPEED=11, DSE=111

Best regards

igor

-----------------------------------------------------------------------------------------------------------------------

Note: If this post answers your question, please click the Correct Answer button. Thank you!

-----------------------------------------------------------------------------------------------------------------------

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mchaplet
Contributor II

Thanks Igor,

You're right !

In fact, my main problem was using the wrong Git repo .... U-Boot fslc has not the same behavior than U-Boot imx.

The "imx" repos (U-Boot and Linux) have much more tweaks and driver support than fslc repos (fsl_otp, Fec2, ...)

Speaking about Linux, do you know how to configure enet_clk_ref in DTS in order to make it generate 50MHz ?

And is it possible to configure GPR1 in dts ? (or I must implement a little hook ?)

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