I'm using imx8mm (PICO PI imx8mm) on my own board. My PHY is KSZ8091, which works in RMII standard.
PHY generates 50Mhz clock on its ref_clk (by doubling 25Mhz clock from its XO pin I guess) pin:
In this other thread, someone was trying to do the same, but on imx6.
However, the pad values at node pinctrl_enet2: enet2grp would be different for me.
How different would it be?
I'd need to change my dts file here:
ubuntu-tn-imx/output/kernel/linux-tn-imx/arch/arm64/boot/dts/freescale/imx8mm-pico.dtsi
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rmii";
phy-handle = <ðphy0>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
};
};
};&iomuxc {
pinctrl-names = "default";
pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
MX8MM_IOMUXC_ENET_RXC_ENET1_RX_ER 0x91
MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x19 /* ENET_nRST */
>;
};
This is what I have currently, and it seems to work. But I'm not convinced this is the right way, for starters, as you can see, there's not even a mention of
MX8MM_IOMUXC_ENET_TD2_ENET1_TX_CLK
Even though the pin, (AG25/ENET_TD2) corresponding to this function, physically connects from MAC side to REF_CLK pin at PHY.
I don't know where is written how MAC side is supposed to receive or send 50Mhz clock in RMII mode, which makes MAC "understand" that TD2 (AG25/ENET_TD2) function is where clock is for RMII, without proper pad configuration in the above mentioned device tree file. If it's "u-boot/u-boot-tn-imx/arch/arm/dts/imx8mm-ddr3l-val.dts", how does it being loaded? How does OS know to load this particular device tree file?
Looking at processor manual and by looking at suggestions in this forum, there seems to be IOMUXC_GPR_GPR1 register which has a relevant field called: "GPR_ENET1_TX_CLK_SEL"
I need it to be set to value 0, because RMII clock comes from "external" PHY.
Where do I set this value? In imx6, here, a guy edited mach-imx6ul.c, namely:
regmap_update_bits(gpr, IOMUXC_GPR1, IMX6UL_GPR1_ENET2_CLK_DIR,
0);
regmap_update_bits(gpr, IOMUXC_GPR1, IMX6UL_GPR1_ENET2_CLOCK_SEL_MASK,
1);
But I have imx8mm, and I couldn't find a relevant file, where is it? Do I make a similar edit?
