RGMII transmission failes on iMX6

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RGMII transmission failes on iMX6

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Martin1z
Contributor III

Hi there,

I am currentry trying the to get ethernet working on a custom iMX6 board where an AR8035 phy is connected via RGMII. MDIO transfers are working properly and I am even able to receivieve ethernet packes (broad-, multicasts). But transmission packages are never sent - even on RGMII bus.

RXC shows a proper clock (which is driven by the phy of course) but unlike on the TXC signal there only is measureable a single low impuse.

IOs are configured correctly (IOMUX and possible daisy chains). Board is connected to a 100MBit network and link is getting detected correcty.

Any ideas what could cause this behaviour?

Is the ref clock (pad ENET_REF_CLK) still required in RGMII mode? This pin is not connected in the current design.

I am appreciating every clue or advice.

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Martin1z
Contributor III

According to the latest hardware manual the RGMII interface is capable to be driven with 2.5V. By increasing this voltage from 1.8V before to 2.5V the RGMII interface is also stable on GBIT links.

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rveer
Contributor II

Hi Martin,

I am facing same clock issue with custom iMX6 board where an marvell switch is connected via RGMII.could you please suggest me, how can I configure to increase voltage from 1.8V to 2.5 V on RGMII line from SoC side?.


Regards

Raj

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Yuri
NXP Employee
NXP Employee

RGMII signals are powered via NVCC_RGMII supply of the i.MX6. So, please take a look at Your design - how
NVCC_RGMII is provided and - if it is possible to change its voltage.

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RobertA
Contributor I

We are facing a similar issue on a custom board.  We have an IMX6q with a KSZ9031RNX phy.  We feed it a 25Mhz clock from a oscillator.  Then from the phy we send the IMX6 a 125Mhz clock to ENET_REF_CLK pin.  Using the same level shifter design as on the reference design.  The NVCC_RGMII and NVCC_ENET port are both connected to 1.8V supply.  I can see in the kernel that the phy is getting discovered, when i set its IP address.  It also recognizes when i switch from 10 to a 100 network.

     root@freescale ~$ ifconfig -a eth0 192.168.1.21 netmask 255.255.255.0

     eth0: Freescale FEC PHY driver [Micrel KSZ9031 Gigabit PHY] (mii_bus:phy_addr=1:01, irq=-1)

     root@freescale ~$ PHY: 1:01 - Link is Up - 10/Half

But when i ping i see activity TX activity on the board i am pinging but i don't receive a packet back.

Do we have to run the NVCC_RGMII port at 2.5V in order for gigabit Ethernet to work?  Or do I have a driver issue.  I modified the current micrel driver to recognize the ksz9021 as the ksz9031 since that are similar.  Do you have any patches that will support a KSZ9031 phy?

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RobertA
Contributor I

We found the problem.  It was not voltage related.  The RGMII from IMX6 to does run at 1.8V for us.  The problem was we had to set the skew registers in the KSZ9031RNX phy.  Once we did that the Ethernet worked. 

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namche
Contributor I

Hi Alex,

Please could you tell me if your PCB clock and data lines were length matched, or whether you added a delay in the clock line as suggested in the Hardware Development Guide?

Best regards

Craig

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RobertA
Contributor I

Hello Craig,

We added a delay as described in the hardware development guide so TX lines, RX Lines each match its grouping.  Then we made sure the clock was proper delayed to these lines as well.  Required us going to our router software and measuring the length of each line and adjusting the skew registers so they matched the hardware development guide.

Best Regards,

Alex

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namche
Contributor I

Thanks Alex! Was it just the TX clock you added delay to, or the RX clock also?

Best regards

Craig

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adeelarshad
Contributor III

Thanks a lot Martin for the quick reply, Ok so modifying the DDR_SEL_RGMII bits in register IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII allow us to increase the driving strength. But I am still not able to transmit the data even on 10/100Mbps network. Experiencing the same issue of low impulse on TXC line. Any suggestions ?

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Martin1z
Contributor III

In our case it was mainly an electrical problem. Whats your input voltage at NVCC_RGMII? Mayeb you should verify if this supply is stable enough. And as mentioned before we need to increase this voltage up to 2.5V for a stable GBit interface between MAC and PHY.

I think that in prior hw manuals NVCC_RGMII was specified with a maximum range up to 1.8V.

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adeelarshad
Contributor III

Well earlier the input voltage at NVCC_RGMII was 1.8 v, but I have tested by increasing it to 3.0 v as well. So what I am understanding here is that due to the low driving strength the i.mx6 is not able to generate the clock output to it RGMII_TXC pin..... correct ? Is there any other reason due to which I am not able to drive it .... Is there some acknowledgement of transmitted data on RGMII lines ?

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Martin1z
Contributor III

The atheros phy offers an option to adjust a clock delay for transmit clock (RGMII_TXC). Maybe your phy also offers such option you could play arround with?

Is the RGMII_CLK generared by your PHY? Is it running at 25MHz or 50MHz?

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adeelarshad
Contributor III

Yes on KSZ9031 we tried to adjust the skew on Transmit clock(RGMII_TXC). The RGMII_TX_CLK is being sourced from ENET whereas the RGMII_RX_CLK is being sourced from PHY. As per the PLL_ENET settings we have ENET clock set up at 50 MHz.

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adeelarshad
Contributor III

Hi Martin,

Thanks for all the help. Actually we have reached to the final conclusion after some more discussion with Freescale that i.mx6 requires a Reference clock externally on ENET_REF_CLK pad and without that it could not work / generate the TX CLK. So we now going with board re-spin to connect the 125 MHz clock from PHY chip to ENET_REF_CLK pad on i.mx6.

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lydia_ziegler
NXP Employee
NXP Employee

Just a note from the Hardware User's Guide:

Designers should be aware of the 125 MHz reference output level of the PHY because ENET_REF_CLK is on the NVCC_ENET supply rail, not the NVCC_RGMII rail. So if NVCC_ENET is powered at 3.3 V, the minimum VIH level is 70% of 3.3 V or 2.3 V. Designers should ensure that there is margin to this minimum value.


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Martin1z
Contributor III

Is there any chance to use 1588 counter as source clock for MAC interface?

Unfortunatly it is not clear to me how the 1588 module is interconnected to the MAC interface yet. For exmaple I also do not see the reason to set GPR1 - bit 12 which is done in  board_init.

#ifdef CONFIG_FEC_1588
    /* Set GPIO_16 input for IEEE-1588 ts_clk and RMII reference clock
     * For MX6 GPR1 bit21 meaning:
     * Bit21:       0 - GPIO_16 pad output
     *              1 - GPIO_16 pad input
     */
    mxc_iomux_set_gpr_register(1, 21, 1, 1);

#endif

According to the reference manual this bit for "MIPI sensor to the IPU2 mux control" ?!

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Martin1z
Contributor III

Meanwhile ethernet is working properly - at least for 100MBit/s. Unfortunatly we still have some problems with GBit configuration where it seems that some packages are gettings lost.

Link is detected correctly and RGMII is configured accordingly in ECR and RCR registers.

Reference clock is 125MHz but the RGMII interface is still running at 25MHz (RGMII).

Does someone have Gbit ethernet working with an ahteros phy?

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adeelarshad
Contributor III

Hi Martin,

I am facing almost the similar issue with KSZ9031. MDIO interface is working correctly as well as the RGMII receive but facing the same issue on the RGMII transmit. How did you managed to get the RGMII transmit working ?

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fabio_estevam
NXP Employee
NXP Employee

Yes, Gbit ethernet works fine on mx6qsabresd board with Atheros PFY

Here is the U-boot patch:

http://git.denx.de/?p=u-boot/u-boot-imx.git;a=commitdiff;h=f6b12ccb690f5533ef7ab0c29bc690e0ce994600;...

Regards,

Fabio Estevam

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Martin1z
Contributor III

Thanks for your quick reply.

After some additional investigations it had turned out that we need to increase the IO-voltage for the RGMII interface in the atheros phy to get a stable gigabit connection between the MAC and the PHY.

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