Hi community,
I have a signal integrity problem on one of our new design.
This board contains a IMX6QP5EYM1AB processor with associated components including DDR3 memory and a Marvell 88E6352 Ethernet switch.
The RGMII_TXC signal (125 MHz clock output from IMX6 processor) is perturbated.
See the attachment file:
fig 1: schematics
Fig 2: RGMII_TXC signal at the 88E6352 device input. The RGMII bus length is about 200mm (8 inches) long.
Fig 3: RGMII_TXC signal zoomed.
Fig 4: RGMII_TXC at the output of IMX6 device. This measurement have been made by isolating the output from the pcb lane (R1888 not populated).
I have establish that this perturbation is synchronous whith DDR3 RZQ calibration.
Is somebody able to help me about this problem ?
Hi Daniel
for rgmii clocks usage one can look at
https://community.nxp.com/message/425444#425444
https://community.nxp.com/message/477655?commentID=477655#comment-477655
Best regards
igor
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Hi Igor,
I made a RGMII_TXC measurement on a SABRE_SCH-27516_REV_C3 evaluation board and observed the same perturbation, always synchronous to DDR3 RZQ calibration
As mentioned in my first post, the RGMII bus length is about 8 inches long on my board, so the signal is more perturbed.
I have tried to modify the drive strength.
This have a slight effect on the rising edge, but creates overshoots and undershoots on the signal.
Again, this phenomenon is only visible when a RZQ calibration occurs.
I also checked all the power supplies involved on IMX6 and DDR3 devices, and did not see anything while RZQ calibration.
Do you have an idea about the relationship between RZQ calibration and RGMII_TXC output ?
Best regards,
Daniel
Hi Daniel
NXP does not use 125MHz reference clock for RGMII interface as i.MX6Q output signal
and recommendation is to use externally provided clock.
Such case (125 MHz clock output from IMX6 processor) was not validated,
so you can observe perturbated waveforms.
Best regards
igor