RAM access slow when downloading u-boot by sb_loader tool

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RAM access slow when downloading u-boot by sb_loader tool

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georgwaibel
Contributor II

Hi,

I have a U-Boot image (no SPL build) that is running well when the board is booting it from eMMC.

When I download the same image into RAM via the USB serial loader protocol (using the sb_loader tool or the imx_usb_loader tool) and start it from there, the U-Boot seems to run properly as well. But RAM access is very slow in this case. I tested this with the mtest command. The writing cycle takes approx. 2 times as long as when booting from eMMC. Reading is even >10 times slower.

Since in both cases the same DCD is used, I do not understand where the difference comes from:

When booting from eMMC, ROM code loads the first portion of the image and applies the DCD. Then it loads the rest of the image to RAM and starts it.

When using the USB loader, the loader tool gets the DCD data from the image and applies it to the CPU. Then it downloads the image and starts it. 

Did anyone come across the same issue?

Regards

Georg

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4 Replies

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matthias_schiffer
Contributor II

Has this ever been resolved? I'm currently seeing the same issue on an i.MX6UL board.

CCM registers look identical for both boot sources. Using the MMDC profiling feature, I've found out that RAM access is so slow because something is causing high numbers of memory accesses:

After booting from SD card, there are very few RAM accesses when idle:

=> mw 21B0410 a; mw 21B0410 1; sleep 1; md 21B0418 4
021b0418: 179b2e3f 00000856 00000017 00000002

Booted from USB serial downloader:

=> mw 21B0410 a; mw 21B0410 1; sleep 1; md 21B0418 4
021b0418: 179b450d 06d02898 000279bf 004e81b4

So we're seeing ~160k read accesses and ~5M write accesses every second. There numbers are fairly stable.

I assume it must be something set up by the boot ROM, but how can I debug further what is causing these accesses?

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matthias_schiffer
Contributor II

After some more research, I was able to find the solution: The old U-Boot version I'm using was missing this patch: imx: Enable ACTLR.SMP bit for all i.MX cortex-a7 platforms (c5437e5b) · Commits · U-Boot / U-Boot · ... 

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georgwaibel
Contributor II

This fixed the issue for me too.

Thanks

Georg

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igorpadykov
NXP Employee
NXP Employee

Hi Georg

sb_loader may change processor clocks, one can check its sources
GitHub - NXPmicro/sb_loader: The tool is used to download an image to Freescale/NXP IMX platform to ... 

So one can dump and compare ccm registers in both cases using Chapter 18 Clock Controller Module (CCM),

Figure 18-2. Clock Tree i.MX6UL Reference Manual

http://www.nxp.com/docs/en/reference-manual/IMX6ULRM.pdf

Best regards
igor
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