Qurey about clock descriptions in mx6 RM.

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Qurey about clock descriptions in mx6 RM.

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simmisxu
Contributor III

Dear guys,

    In mx6Q/D RM, charpter 18.4 System Clocks, there is the clome "clock" in the table.

    For many clock names in this table, like clocks for usduc hclk, ipg_clk_perclk, ipg_clk_s, I can not find any descriptions no matter in RM or in kernel code.

    In my opinion, the name of "hclk", whose root clock is ahb_clk_root , should be "ahb" in kernel code mach-mx6/clock.c.

    I wonder this is RM errors or there are some others deep meanings?

 

   Currently I want to find out ways of adjusting EMMC clock. I think the clock should be  ipg_clk_perclk, corresponding to usdhc_clock_root. Am I right?

Thanks,

Simmis.

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tonyzheng
NXP Employee
NXP Employee

Hi,

I think EMMC clocks derive from USDHCn_CLK_ROOT. For example USDHC1_CLK_ROOT,if you want to adjust it, you can modify CSCDR1: usdhcn_podf and CSCMR1: usdhc1_clk_sel register.

CSCDR1: usdhcn_podf: 3-bits divider for usdhc3 clock podf

000 divide by 1

001 divide by 2 (default)

010 divide by 3

011 divide by 4

100 divide by 5

101 divide by 6

110 divide by 7

111 divide by 8

CSCMR1: usdhc1_clk_sel: 1-bit selector for usdhc1 clock multiplexer

0 derive clock from 396M PFD

1 derive clock from 352M PFD

Hope to help you!

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simmisxu
Contributor III

Hi Tao,

     Thanks for your info.

     Actually I also know the register. But I need to step forward, at least 2 points:

    1. Which part of usdhc-related clock system is changed after setting register. Figure 67-2, Figure 67-11 both describ some part of clocks.

    2. As previous commented, I doubt RM has some errors, that "hclk" shold be "ahb" in mach-mx6/clocks. This is nontrivial for understanding mx6 clock tree.

        According to Figure 67-1, I think AHB bus, IP bus, card slot all need seperate clocks that should be in Table 67-5.

    I need to figure out all of these. RM is some kind of bewildering!

Thanks,

Simmis.

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tonyzheng
NXP Employee
NXP Employee

Hi, Simmis

For first question:

In Figure 67-2. (ultra Secure Digital Host Controller Block Diagram), ipg_clk/ipg_clk_s/ahb_clk are the SOC clock domains, we don't need to focus on it in software development. When we change usdhc-related clocks, such as CSCDRn and CSCMRn, the bus clock (AHB and IPS) don't change, the only changed clock is usdhc_clk_root. Unless you are sure what you are doing, don't try to change system bus clock. Because system bus clock is used by many modules, not only usdhc module.

For second question:

As just discussed, hclk is SOC clock domain, don't correspond to linux clock system. So, I don't think that "hclk" shold be "ahb" in mach-mx6/clocks.

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simmisxu
Contributor III

I think usdhc root clk can be ajusted by CCM_CSCDR1. While the usdhc output clk can be changed by uSDHCx_SYS_CTRL.

Anyway, if it is possiable, I still hope to know more about "Clock name" of each module in RM.

Thanks.

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tonyzheng
NXP Employee
NXP Employee

Hello,

I have the same doubts about clock systems. In my opinion, clocks like usduc hclk, ipg_clk_perclk, ipg_clk_s are physical signal used by SOC design, and invisible to board-level developers.

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