Question, i.MX8M minimum CPU clock

[SLICE]

Dear team,

I would like to ask about the minimum clock speed of i.MX8M.

Could you show me what is the minimum clock speed of i.MX8M(Cortex-A53 and Cortex-M4).

The customer wants to know what numbers are available to scale down dynamically.

They think it must be related to the DDR clock.

Best Regards,

Miyamoto

[SLICE]

Hello pengtian‌

I executed the command you suggested on my 8M-EVK with L4.14.78-BSP.

And the messages are as below.

Max:

1500000

1500000

1500000

1500000

Min:

1000000

1000000

1000000

1000000

Does those mean that the max speed of cortex-A53s are 1.5GHz?

And does those mean that the Min speed of cortex-A53s are 1.0GHz?

How about the min frequency of cortex-M4?

Best Regards,

Miyamoto

[peter_tian]

Hello Miyamoto,

Yes. These values you got are max_freq (1.5GHz) and min_freq (1.0GHz) on i.MX8MQ-EVK + L4.14.78-BSP.

CPU (Cortex-A53) frequencies can be scaled automatically between min_freq and max_freq depending on the system load.
The target frequency of Cortex-M4 platform is 266 MHz. And there is no frequency scale function for Cortex-M4 platform.

Best Regards,

Peter

[SLICE]

Hello Peter,

Thanks for your support.

Can I understand that CA53’s minimum frequency is 1.0GHz theoretically?

And CM4 cannot scale down from 266MHz.

Correct?

Best Regards,

Miyamoto

[peter_tian]

Hello Miyamoto,

You can get the freq-points supported on current platform.  Release BSP doesn't support others frequencies except them. Can you understand it?

cat /sys/devices/system/cpu/*/cpufreq/scaling_available_governors

CM4 core is designed at the target of 266MHz.

Best Regards,

Peter

[SLICE]

Hello pengtian‌

Can I understand that min freq of CA53 is 1GHz and min freq of CM4 is 266MHZ?

We want to know the theoretical minimum freq of CA53 and CM4 to reduce power.

Best Regards,

Miyamoto

[peter_tian]

Hello Miyamoto,

There is no limitation on the minimal frequency, any frequency below the target defined for the operating PVT should be supported. Customers also need to balance overall system performance and power consumption. Thanks.

Best Regards,

Peter

[SLICE]

Hello Peter,

Can I understand as below?

Theoretically, the minimum frequency of CA53 and CM4 is no limitation in the terms of chip.

But the customer need to develop their own device driver for down scaling the frequency when they use the other OS than your BSPs.

Best Regards,

Miyamoto

[peter_tian]

Hello Miyamoto,

Yes. Customers need to re-make their device driver to down scaling the frequency which cannot be supported by NXP release BSP. Thanks.

Best Regards,

Peter

[peter_tian]

Hello Miyamoto,

To check the maximum frequency:
cat /sys/devices/system/cpu/*/cpufreq/cpuinfo_max_freq

To check the minimum frequency:
cat /sys/devices/system/cpu/*/cpufreq/cpuinfo_min_freq

The system automatically adjusts DDR frequency for optimal performance based on the devices that are active.

Best Regards,

Peter