Question, i.MX6S ESAI SSI

[Aemj]

Dear All,

I would like to ask about ESAI and SSI features.

(1)

Is it possible for ESAI to handle different format audio data, such like I2S, 8slot TDM and so on, simultaneously?

In my customer’s understanding, it is not possible for i.MX6 ESAI to handle different formats simultaneously because High Frequency Clock Divider cannot specify bitclocks per each port.

Is the customer’s understanding correct?

Do you have any solutions to handle different audio format data that has different bit clocks simultaneously?

(2)

For SSI,

The customer believes that the each of SSIs(SSI1, SSI2 and SSI3) can be configured with different slot and clock divider independently.

Then he believes SSIs can be used with different audio format per ports simultaneously, such as;

SSI1 = I2S, SS2 = 8slot TDM

Is it true?

BR,

Miyamoto

[Yuri]

1.
  The ESAI provides a full-duplex serial port. Generally it is a single port ; in this sense it is not similar

to the AUDMUX, which supports multiports, working simultaneously.  In the same time, the ESAI consists

of independent transmitter and receiver sections, each section with its own clock generator; this
means the transmitter and receiver may work as two separate channels.

2.You are right - the SSI(s) may be configured fully independently.

[Aemj]

Hi Yuri,

I mean that the customer wants to set independent bit-clock per TX0-5 or per RX0-3.

Does it make sense?

[Yuri]

"When SYN is cleared, the ESAI transmitter and receiver clocks and frame sync sources

are independent. If SYN is set, the ESAI transmitter and receiver clocks and frame sync

come from the transmitter section (either external or internal sources)." So, basically

it is possible to have different frequencies.

[Aemj]

Hi Yuri,

For (1);

In my customer’s understanding, High Frequency Clock Divider which should be set by ESAI_RCCR and ESAI_TCCR registers cannot be configured per each section independently.

From the above, the bit-clocks of the each section shall be the same.

Correct?

Miyamoto

[Yuri]

Yes, "In the synchronous mode (SYN=1), the bit clock defined for the transmitter

determines the receiver bit clock as well."