Question, i.MX6Q android/ reboot command

[Aemj]

Dear team,

My customer is using i.MX6Q for their board and OS is your android BSP base.

This is a quick question from the customer.

They use ‘reboot’ command from terminal to restart the board, and sometimes it does not work correctly and it causes the hang.

Could you show me what is actually executed by ‘reboot’ command?

Jumping to Boot loader? Or accessing internal registers to reset the i.MX6?

Thanks,

Miyamoto

[CarlosCasillas]

Hi,

Have you checked which TO do you have on your board? Board with TO1.1 does not allow reboots from an android system. Board with TO >= 1.2 does.

Additionally, you could check the recommendations from the following thread:

https://community.freescale.com/message/407787

Hope this will be useful for you.
Best regards!
/Carlos

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[Aemj]

Dear Carlos,

Could you show me why the Rev.1 chip does not allow reboot?

The customer think WDOG reset mechanism is related.

BR,

Miyamoto

[CarlosCasillas]

Hi,

You could refer to ERR005768 of the IMX6DQCE document at this link, WDOG is also related.

Hope this will be useful for you.
Best regards!
/Carlos

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[Aemj]

Hu Carlos,

I am still confused.

In the errata(IMX6DQCE Rev.4), there is no ‘Fixed’ for ERR005768 and it seems to exist on latest revision chip.

Is ERR005768 the reason why the Rev.1 chip does not allow reboot?

BR,

Miyamoto

[CarlosCasillas]

Hi,

I need to confirm these details.

Could you please tell me which silicon version are you using?

I will be waiting for your reply. Best regards!

/Carlos

[Aemj]

Hi Carlos,

The parts# is MCIMX6Q5EYM10AC.

Actually, the customer’s board does not use WDOG_B pin and rest from external never happen.

The customer tried to modify source code (system.c) as below.

Changing the number of times (twice or three times) of writing to wdog_base;

  __raw_writew(wcr_enable, wdog_base);

Changing the time value of mdelay.

Can resetting CPU be achieved by writing to wdog_base(__raw_writew)?

BR,

Miyamoto

[CarlosCasillas]

Hi,

ERR005768 looks about recovery image, and it would not be related with reset function. MCIMX6Q5EYM10AC is Rev. 1.2, so reset issue is not related with TO1.1.

Based on i.MX6DQ SabreSD design, WDOG_B is used to POR_B to PMIC. With SRS asserted, PMIC powers cycle CPU. If WDOG_B IOMUX is not configured, SRS doesn't trigger POR_B, and PMIC won't power cycle CPU. Then reboot doesn't happen.

Hope this will be useful for you.
Best regards!
/Carlos

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Note: If this post answers your question, please click the Correct Answer button. Thank you!
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[Aemj]

Dear Carlos,

On the customer’s board, the circuit design around PMIC and i.MX6 is not same as SABRE board. When the reboot command is executed, i.MX6 does not kick PMIC on the customer’s board.

In the customer’s understanding, setting WDE bit of WDOGx_WCR register can reset i.MX6 internally. Is it true?

Please let me know what is exactly done internally in i.MX6 by setting WDE bit?

And could you show me the right way to reset i.MX6 internally?

BR,

Miyamoto

[Aemj]

Hi Carlos,

I still wait for your comment.

Thanks,

Miyamoto

[CarlosCasillas]

Hi,

Based on the Reference Manual, the WDE bit of WDOGx_WCR just enables/diables the watchdog with some caveats. See Chapter 70.6.2 of the Reference Manual (IMX6QRM.pdf) for details.

There are a variety of ways to reset the i.MX6Q. Chapter 70 is full of several reset scenarios via the watchdog. Experts are researching and they will provide some options soon.

Hope this will be useful for you.
Best regards!
/Carlos

[Aemj]

Hi Carlos,

Thanks for your comment.

From the fact that setting WDE bit can cause reboot on their board despite of not using WDOG signal, the customer believes that some other things other than what reference manual says will be executed by setting WDE bit.

They think it can reset CPU internally.

Is it true?

I will wait for your expert’s comment.

BestRegards,

Miyamoto

[CarlosCasillas]

Hi, sorry for the delay.

Experts have commented that according with documentation, WDBG (debug) must be enabled (which suspends the watchdog timer) before the WDE can be disabled/enabled (section 70.6.2 of the RM).

Other notes indicate that if other bits are enabled  the watchdog disable does not occur and if not update or the timer is made beforehand, the watchdog will time out and 'fire'.

Hope this will be useful for you.
Best regards!
/Carlos

[Aemj]

Hi Carlos,

Tanks for your reply.

Can I understand that one has to set WDBG bit (Suspend the watchdog timer by set WDBG) before WDE bit operation for reboot internally?

Thanks,

Miyamoto

[CarlosCasillas]

Hi,

It seems that it indicates that the bit can be 'set/reset' in debug mode.

In the documentation it states this, although not highlighted, for the WDE bit (See pages 5770-5771 of 6Q reference manual). it says:

NOTE:    This bit can be set/reset in debug mode (exception).

If the watchdog is running it seems irrelevant to reprogram any operational bit unless the watchdog is in a known acquired state. Reprogramming 'on the fly' may incite undesired consequences.  In this case it seems proper to suspend/disable the watchdog, modify its registers, and restart it once reprogrammed.

Best regards!

/Carlos

[Aemj]

Hi Carlos,

Thanks again.

I understand that the correct way to reset i.MX6 is;

Set WDBG bit.

Then set WDE bit.

Correct?

BR,

Miyamoto

[Aemj]

Hi Carlos,

Setting WDBG bit makes watchdog timer suspend.

Does Wdog work by setting WDE bit even after suspend the timer?

I feel wdog cannot work without the timer running.

BR,

Miyamoto

[Aemj]

Hi Carlos,

The customer is still waiting for your comment.

Is it possible for i.MX6 to reboot by setting WDE even when the timer timer is suspended by setting WDBG bit?

Thanks,

Miyamoto

[CarlosCasillas]

Hi,

I just receive an update from AE team:

If someone wants to modify any of the watchdog settings they must suspend/disable it, do the modifications, and then enable it again.  The watchdog will not work without some value in the timer as that is its purpose.  It watches for a specific condition (like a CPU caught in a loop) and if triggered will do something (like reset the CPU) depending on the settings.

Additional details are included on the chapter already highlighted, or looking at the code in u-boot that deals with the watchdog's setup.

Hope this will be useful for you.
Best regards!
/Carlos

[Aemj]

Hi Carlos,

My point is;

WDBG bit is write once-only bit.

If user wants to modify WDE bit, I believe the following sequence is needed.

- Set WDBG bit

- Set WDE bit.

Because WDBG bit is write-once, user cannot clear WDBG to continue WDOG timer operation(exit from debug mode).

Can I understand that setting WDE bit after setting WDBG bit makes WDOG timer run?

What should be done to continue WDOG operation?

BR,

Miyamoto

[Aemj]

Hi Carlos,

I am still waiting for your reply.

According to your Android4.0 release note, it is said that "The loopback reboot test may cause failure".

The customer wants to know how this loopback test failure can be solved.

could you show me?

BR,

Miyamoto