Question, i.MX6DQ I2C clock setting

[Aemj]

Hi Team,

I would like to ask about I2C clock setting.

My customer is trying to set I2C SCL clock frequency to 400KHz but cannot yet.

Now, the customer’s setting is as follows.

- CCM_CBCMR[PRE_PERIPH_CLK_SEL] = 00 (derive clock from PLL2 main 528MHz clock),

- CCM_CBCDR[AHB_PODF] = 011 (divide by 4),

- CCM_CBCDR[IPG_PODF] = 01 (divide by 2),

- CSCMR1[PERCLK_PODF] = 00000 (divide by 1)

Then PERCLK_CLK_ROOT is supposed to be 66MHz.

- IFDR=0x30 (66MHz / 400KHz = 160, IFDR=0x30)

As the result, I2C SCL clock was about 37KHz by the above settings.

Are there any misunderstandings on the above setting to set I2C SCL clock into 400KHz?

Please let me know the correct settings for 400KHz I2C SCL clock.

BR,

Miyamoto

[Yuri]

Please use the iMX6 Platform SDK. It  contains an example how to configure I2C and descriptions about it

in Chapter 16 (Configuring the I2C Controller as a Master Device) of "iMX6_Firmware_Guide.pdf".

https://www.freescale.com/webapp/Download?colCode=i.MX6_PLATFORM_SDK&location=null

[Aemj]

Hi Yuri,

The customer is developing their software based on your LinuxBSP.

He looked at the source code(i2c-imx.c) in LinuxBSP and he found i2c_clk_rate value returned from clk_get_rate() function is 6MHz.

Is the 6MHz value is reasonable?

It is not possible to set I2C clock into 400MHz in the case of 6MHz of i2c_clk_rate value.

And he found the 6MHz clock is set in clock.c, then he modified the code to change it to 11MHz.

He has a concern that the clock modification may affect other module than I2C.

Is it possible for you to show me whether the modification causes problems on the other modules?

BR,

Miyamoto

[jimmychan · Accepted solution]

I2C needs a minimum of 12.8MHz as its source to acheive 400KHz speed. IPG_PERCLK sources I2C. 22MHz when divided by the I2C divider gives the freq closest to 400KHz.

clk_set_rate(&ipg_perclk, 22000000);