Question, i.MX51 Display clock setting

[Aemj]

Dear team,

I would like to ask bout DSP_CLK setting of i.MX51.

My customer wants to change DSP_CLK setting of i.MX51.

Now they are using display interface of i.MX51 to output display data with DSP_CLK’s FALLING edge.

And they want to change it to output display data with DSP_CLK’s RISING edge.

It is possible?

They are using your LinuxBSP(L.2.6.31 base) and they believe that they should modify the source code as below to achieve that.

In source file ipu_common.c, and in ipu_pixel_clk_set_rate() function,

_raw_writel((dev/16)<< 16, DI_BS_CLKGEN1(clk->id));

The above statement should change as below;

_raw_writel(((dev/16)*2)<< 16 | (dev/16) , DI_BS_CLKGEN1(clk->id));

Is it true?

Thanks,

Miyamoto

[igorpadykov · Accepted solution]

Hi Miyamoto

display clock polarity can be changed with register DI0_GENERAL,
bit - 17 di0_polarity_disp_clk DI0 Output Clock’s polarity, described in
Table 42-201. DI0_GENERAL Field Descriptions i.MX51 Reference Manual
http://www.freescale.com/files/dsp/doc/ref_manual/MCIMX51RM.pdf
Setting can be added to ipu_probe() (example of DI_GENERAL usage
can be found in function _ipu_pixel_clk_set_parent)

Best regards
igor
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