Question, i.MX28 DDR2 signal

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Question, i.MX28 DDR2 signal

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Aemj
Contributor IV

Dear team,

My customer is facing the issue that DDR signals have the large overshoot and undershoot on their custom i.MX28 board.

The undershoot and the overshoot are seen on the signals that come from external DDR2.

As for the signals which flow out from i.MX28, there is no problem.

The customer thought that the issue can be improved by enabling the internal registers in i.MX28 for terminate signals by setting HW_PINCTRL_EMI_ODT_CTRL register.

And they tried the following settings, but the results were the same.

- HW_PINCTRL_EMI_ODT_CTRL = 08889999

- HW_PINCTRL_EMI_ODT_CTRL = 08888888

- HW_PINCTRL_EMI_ODT_CTRL = 0888AAAA

- HW_PINCTRL_EMI_ODT_CTRL = 08888899

They thinks that the above settings did not take effect on the impedance of the ports.

For setting the terminate register value, are there any other settings needed?

Thanks,

Miyamoto

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Yuri
NXP TechSupport
NXP TechSupport

Hello,

   Please try to configure drive strength of external DDRs via (memory) Mode
Register Set commands during memory initialization.


Have a great day,
Yuri

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Aemj
Contributor IV

Hi Yuri,

Thanks for your support.

The customer already tried to re-configure the drive strength of DDR side by modifying the register inside of DDRs.

As the result, the issue was improved a little but more adjustment is needed.

They saw the signals had not changed despite of modifying the HW_PINCTRL_EMI_ODT_CTRL register value.

Do you have any ideas about that?

Thanks,

Miyamoto

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Yuri
NXP TechSupport
NXP TechSupport

Hello,

   As for HW_PINCTRL_EMI_ODT_CTRL, You can use only SLICE1 and SLICE2 bit fields,

assuming dynamic termination in HW_DRAM_CTL75 (and HW_DRAM_CTL76) is enabled.

Regards,

Yuri.

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