Question, i.MX25 WEIM timimng

[Aemj]

Dear team,

I would like to ask about WEIM timing of i.MX257.

As for read accessing;

(1)

According to Figure49-7 in i.MX25 reference manual, it is shown that 2 cycles of wait time is inserted by setting WSC=1.

Can I understand that the number of inserted wait cycles is defined as WSC+1?

(2)

Can I understand that i.MX25 samples a read data at the point where I wrote ‘(2) End’ in the attached figure?

(3)

Can I understand that the time from the point of ‘Start’ till Valid Address equals to '1/2*HCLK + WE31'?

As for write accessing;

(4)

Could you show me how to calculate the time of ‘write pulse width’ (the period of WE=L)?

(5)

Could you show me how to calculate the ‘Data set-up time’ and ‘Data hold time’ which I wrote in the attached file?

Thanks,

Miyamoto

[Yuri]

Hello,

  Please look at my comments below.

1.
Use Table 49-10 (WSC Bit Field Values) of the i.MX25 RM.

2.

  According to section 49.4.12 (Internal Input Data Capture) of the RM :

“In the typical case the input data is not sampled by the WEIM, but it is sampled by the AHB master on the rising edge of HCLK when HREADY is high. WEIM asserts the HREADY signal to the AHB master (according to the WSC or DOL counting correspondingly).”

  So, You are right : data are sampled at the point ‘(2) End’.

3.
Time from ‘Start’ till Valid Address is WE4 (refer to the Datasheet [Hardware Specs]).

WE31 (CS[x] valid to Address Valid) = WE4 – WE6 – CSA

WE6 is Clock rise/fall to CS[x] valid.

In particular, for Figure 49-7 : ‘Start’ till Valid Address equals to '1/2*HCLK + WE31'.

4.

  Behavior of RW signal (it is used as WE) is affected by the RWA and RWN fields in the Chip Select control registers. From hardware point of view, parameters WE8 and WE9 also

should be involved. If RWA and RWN are zero, RW is asserted practically during all access

cycle.

5.
Strictly speaking, terms data setup and hold concern with read access, for write - delays

are considered. Parameters WE17, WE17 define timings. For non-multiplexing address / data case, data are asserted during all access cycle.

Have a great day,

Yuri

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