Question about how to achieve the maximum mipi csi2 bandwidth of 800Mbps with 4-lanes

[eason-tang]

Hi :

I met a problem about mipi csi2 maximum bandwidth on imx6.

I know 800Mbps per lane with 4-lanes is the maximum in theory.

My problem has been committed in IMX6 mipi CSI2 sensor display on HDMI issue .

Now my question is:

1 Could imx6 mipi csi2 bandwidth rate achieve the maximum 800Mbps per lane FULLY with 4-lanes ?

2 If it could achieve,How to configure it ?

My project hardware environment is imx6 mipi 4lanes receive + TIUB964 de-serializer 4lanes 800Mbps/lane output.

My problem could disappear in using this ways below:

1 Configure imx6 mipi 3lanes receive + TIUB964 de-serializer 3lanes 800Mbps/lane output.

2 Configure imx6 mipi 2lanes receive + TIUB964 de-serializer 2lanes 800Mbps/lane output.

3 Configure imx6 mipi 4lanes receive + TIUB964 de-serializer 4lanes 400Mbps/lane output.

So I want to know How to configure imx6 mipi to achieve the maximum 800Mbps per lane FULLY with 4-lanes ?

Qingcai

[igorpadykov]

Hi Qingcai

from hardware point of view there is no special configuration for such use case.

However performance may depend on bus loading and it is application dependent.

NXP has special service for helping with such cases:

Professional Engineering Services | NXP 

Best regards
igor
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[eason-tang]

Hi igorpadykov‌:

My question also has been found in freescale official EVB board.

So I want to find the root cause.

Could you tell me how to get your Professional Engineering Services ?

Do I need to pay for some money?

Could you help me to loop someone to discuss my problem?

I will send my e-mail to you.

Thank you very very very much.

[igorpadykov]

for Professional Engineering Services please fill form below

Professional Services Software Technologies Form | NXP Semiconductors 

Best regards
igor