Question about detecting UART break condition

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Question about detecting UART break condition

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RoyKang
Contributor II

Hi, I am using i.MX8MP and have a question about detecting UART break conditon.

In my testbed, i.MX8MP only recieve packet from packet sender. The packet sender make break condition like below:

RoyKang_0-1737585669867.png

When using UART with DMA, the break condition is detected, but without DMA, it is not detected.

Can you let me know why can't detect break condition without DMA?

Thanks,

Roy.

 

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Manuel_Salas
NXP TechSupport
NXP TechSupport

Hello @RoyKang 

I hope you are doing very well.

 

Could you please share more details? Also, how can I replicate your issue?

Are you using Cortex A (Linux OS)? Cortex M (SDK)?

If using Linux, please share your BSP version.

 

Best regards,

Salas.

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RoyKang
Contributor II
Hi, @Manuel_Salas
I hope you’re doing great too.

I'm using Cortex A (Linux OS, BSP 5.10.72).

Thanks,
Roy.
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Manuel_Salas
NXP TechSupport
NXP TechSupport

Hello @RoyKang 

 

Digging a little in this topic, I found the imx_uart_start_rx(struct uart_port *port) , and I saw in that function is configured the UART to works like DMA or without DMA.

If DMA is not enabled:

ucr1 |= UCR1_RRDYEN;
ucr2 |= UCR2_ATEN;

 

RRDYEN: Receiver Ready Interrupt Enable. Enables/Disables the RRDY interrupt when the RxFIFO contains data. The fill level in the RxFIFO at which an interrupt is generated is controlled by the RXTL bits. When RRDYEN is negated, the receiver ready interrupt is disabled.

  • 0 Disables the RRDY interrupt.
  • 1 Enables the RRDY interrupt.
 
 

ATEN: Aging Timer Enable. This bit is used to enable the aging timer interrupt (triggered with AGTIM).

  • 0 AGTIM interrupt disabled
  • 1 AGTIM interrupt enabled
 

One can try to enable BKEN in UCR4.

BKEN: BREAK Condition Detected Interrupt Enable. Enables/Disables the BRCD bit to generate an interrupt.

  • 0 Disable the BRCD interrupt
  • 1 Enable the BRCD interrupt
 

Best regards,

Salas.

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RoyKang
Contributor II

Hi, @Manuel_Salas .

The source code has been changed as follows:

2025-02-03 15 36 55.jpg

Control registers value is:

  • With DMA
    • UCR1 : 0x0000 0125
    • UCR2 : 0x0000 5027
    • UCR3 : 0x0000 038C
    • UCR4 : 0x0000 4006
  • Without DMA
    • UCR1 : 0x0000 0221
    • UCR2 : 0x0000 502F
    • UCR3 : 0x0000 038C
    • UCR4 : 0x0000 4006

I think BKEN was enabled but break condition is not occurred without DMA. (occurred with DMA).

Test environment:

PC <--- USB to 485/422 converter ---> HBU-208B NMEA splitter (please refer attached file) <--- RS232 cable ---> iMX8MP B/D

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RoyKang
Contributor II

I forgot to attach a file.

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