Question about I.MX6 Dual lite to DDR3 RAM RESET_B of Line Length

[inhojeon]

I wondering about Line Length of  I.MX6 Dual lite to DDR3 RAM RESET_B.

[art]

Since DRAM_RESET_B is relatively slow and asynchronous signal, there is no strict limitation on its trace length. However, the good practice for routing this signal is to not exceed the maximum SDCLK trace length.

Have a great day,
Artur

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