Question about DDR memory bandwidth of i.MX8MNano

[ko-hey]

Hi everyone,

I would like to know the DDR memory bandwidth of i.MX8MNano.

Q1.

Generally, users should set the bus priority to achieve high efficiency memory bandwidth.

Can i.MX8MNano set the DDR bus priority by user ? Or Is it fixed ?

Q2.

Do you have any data for measured value of DDR bus bandwidth ?

Q3.

If Q2 is no, how much should I estimate the measured value ?

I guess it's about 30-40% of theoretical value. Do you agree with it ?

Ko-hey

[art · Accepted solution]

1. The DDR bus priority of the i.MX8MNano processor is fixed to the highest one.

2. No, we don't have any measured numbers of the i.MX8MNano DDR bus bandwidth.

3. Typically, the real DDR bus bandwidth is about the half of the theoretical one.

Best Regards,

Artur