Question about BOOT_CFGx in i.MX6DL

[ko-hey]

Hi all

I have some question about BOOT_CFGx registers in i.MX6DL.

I can't understand the purpose and how to select it.

So please tell me following questions.

Q1."SD Calibration Step inn P.335 Table5-5 BOOT_CFG2[7:6]"

What is the purpose of SD Calibration Step ?

I can't imagine the calibration for SD.

What kind of information do you choose based on ?

Q2. "DDR Memory Map default config in P.335 Table5-5 BOOT_CFG3[5:4]"

What is the purpose of the register ?

What kind of information do you choose based on ?

Q3."DLL Override in P.335 Table5-5 BOOT_CFG2[2]"

What is the Boot ROM default value ?

What kind of information do you choose based on ?

Ko-hey

[Yuri]

Hello,

1.

  According to section 8.5.3.3 (SD, eSD, and SDXC) of i.MX6 S/DL RM,

The UHSI calibration start value (MMC_DLL_DLY[6:0]) and the step value

(BOOT_CFG2[7:5]) can be set to optimize the sample point tuning process.

It is needed to support high speed modes. Please look at section 67.5.3.2.4

[DLL (Delay Line) in Read Path] of the RM.

2.

  DDR Memory Map default option relates to memory configuration; the MMDC
supports two channel LPDDR2.

3.

 SD calibration is performed by ROM code, users typically don't need to override

this value, When BOOT_CF2[DLL ovirride] bit is set, the value at associated

DLL_DLY value is applied. Refer to the item 1.

Have a great day,
Yuri

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[ko-hey]

Hi Yuri Muhin

Sorry for late reply.

I have an additional question about No.3.

> SD calibration is performed by ROM code, user typically don't need to override

> this value, When BOOT_CF2[DLL ovirride] bit is set, the value at associated

> DLL_DLY value is applied. Refer to the item 1.

Could you give me an example situation when user need to override the value ?

Ko-hey

[Yuri]

Hello,

  from the design checklist at HW_Design_Checking_List_for_i.MX6DQP6DQ6SDL 

(sheet "issue hunting"): 

0x450[10](BOOT_CFG2) DLL Override: 0 - Boot ROM default 1 - Apply value per fuse field MMC_DLL_DLY[3:0]
Default setting in ROM is incompatible with current PCB design.

Set 0x450[10](BOOT_CFG2) to "1", and try to find proper setting through fine tune related FUSE.

Regards,

Yuri.

[ko-hey]

Hi YuriMuhin_ng‌

How to judge the proper setting ?

Is it judge by waveform ?

I can't understand whether what is proper or not.

Ko-hey

[Yuri]

Hello,

  Here situation is similar to memory calibration: it is needed 

to get range of the values, where  operations are good for 
several boards and choose, say, the median value. 

Regards,

Yuri.

[ko-hey]

Hi Yuri Muhin

Thank you.

Ko-hey