Question, LDO settings of i.MX6SDL

[SLICE]

Dear team,

My customer has some questions on the description of datasheet of i.MX8SDL(IMX6SDLCEC, Rev.8).

In that datasheet, from the notes.3 to 5 of Table.8 ‘Operating Range’ mentions about the restrictions of its LDO settings.

Could you show me why the restrictions are specified?

From the statements, they feel the settings between other LDOs has some relations.

Is it true?

If so, why the relationship exist?

And please let me know what issues could be seen if one does not comply the restrictions.

Thanks,

Miyamoto

[igorpadykov · Accepted solution]

Hi Miyamoto

seems restrictions are specified due to level shifters requirements between VDD_ARM and
VDD_SOC power domains, one can look at Figure 10-10 Isolation cells and Voltage level
shifters placing i.MX6SDL Reference Manual
http://www.nxp.com/assets/documents/data/en/reference-manuals/IMX6SDLRM.pdf
VDD_SOC LDO output set point is equal to the VDD_PU LDO, since there is no
level shifter between SOC and PU domains.

>From the statements, they feel the settings between other LDOs has some relations.
>Is it true?

there are no other restrictions except described in footnotes to Table.8 Operating Range.

>And please let me know what issues could be seen if one does not comply the restrictions.

this may affect chip reliability and formally described in sect.4.1.1 Absolute Maximum Ratings
i.MX6SDL Datasheet:

Functional operation of the device at these or any other conditions beyond those indicated
under “recommended operating conditions” is not implied.

http://www.nxp.com/docs/en/data-sheet/IMX6SDLCEC.pdf

Best regards
igor
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