Question, LDO setting of i.MX6SoloLite

[Aemj]

Dear team,

I would like to ask about LDO setting of i.MX6SoloLite.

My customer is trying to re-check their LDO settings based on i.MX6SoloLite datasheet.

(1)

In Table 9 ‘Operating Ranges’ in i.MX6DL DS(IMX6SLCEC, Rev.4), the following comments are written.

“LDO output set at 1.250V minimum for operation up to 996 MHz”.

Also for the other VDD_ARM_IN voltages of RUN mode, similar statements are written in comment columns.

Does the 1.250V mean the minimum voltage?

Otherwise, could you show me the meaning of the 1.250V?

(2)

After reading Table9 in the datasheet and its notes, they think that LDO voltage setting register should be 00000 (gated off) because they do not use PU. But according to the note (VDD_SOC_CAP and VDD_PU_CAP must be equal.) of the Table 9, they think the setting may not be 0.

Could you show me which one is correct?

(3)

As for the note-2 and note-4 written in the Table-9;

Should one obey the note2 and note4 even when the voltages are set to intermediate value not minimum nor maximum?

(4)

As for the formula written in note4 of the Table-9, VDD_ARM - VDD_SOC / VDD_PU < 50mV;

Is the ‘/’ mean division operator?

And can I understand that the formula is as below?

(VDD_ARM – (VDD_SOC / VDD_PU) ) < 50mV

(5)

After reading DS, they think the following settings can be used for their system.

	LDO_ARM	LDO_SOC	LDO_PU	VDD_ARM	VDD_SoC VDD_PU
996MHz	1250mV	1250mV	0	1375mV	1375mV
792MHz	1150mV	1150mV	0	1275mV	1275mV
600MHz	1050mV	1050mV	0	1175mV	1175mV

Is the above correct?

On the other hand, they read your LinuxBSP source and it configures as below.

	LDO_ARM	LDO_SOC	LDO_PU	VDD_ARM	VDD_SoC VDD_PU
996MHz	1250mV	1250mV	0	1375mV	1375mV
792MHz	1150mV	1175mV	0	1275mV	1300mV
600MHz	1050mV	1175mV	0	1175mV	1300mV

They believe that the above settings do not match the description in DS.

Could you give your comment on that?

Thanks,

Miyamoto

[RossMcLuckie · Accepted solution]

Hi Miyamoto,

Let me try to help, some of this is not as clear and easy to understand as it should be.

For 1. The minimum set points defined in the datasheet are for LDO enabled mode and are the minimum set point that should be used to support the defined frequency of operation. The LDO set points step in 25mV volts, so if you take the example for 996MHz there are two valid settings for the LDO 1.25 and 1.275 (1.3 is not a valid set point).

For 2. If the GPU is in use, requiring the PU LDO to be on, then SOC_CAP must equal PU_CAP, if there is no GPU in use, or you are using a part without a GPU, then this can be power gated and LDO PU can be off.

For 3. Yes the rules must be followed, the ARM_IN and SOC_IN must be at least 125mV greater then their associated _CAP set point, note 4 must also be followed, further explanation follows.

For 4. This is unfortunately very confusing, it is not a divide by sign and not really a formula, it should read VDD_ARM should not exceed VDD_SOC or VDD_PU by more than 50 mV. Note 3 states SOC_CAP must equal PU_CAP, if in use, the exception is if there is no GPU in use, then PU_CAP can be 0

For 5. I assume LDO_ labels refer to the _CAP levels and VDD_ labels refer to the _IN levels. Looking at the customer table it looks like they have calculated a set point for 600 MHz operation, that set point is not defined in the datasheet, customer can do that if they wish, but they would need to fully validate this, we will only guarantee our datasheet set points and these are the only points our BSP team will use e.g. for 600 MHz, closest set point in datasheet is 792 MHz, so that is what they will use. I don't know the details why the 1175 mV set point has been used for SOC_CAP, it may be some margin that has been added, but it is within spec and meets all the required rules, 1150 mV may work fine, but I would recommend following the BSP settings as these are what we have validated the operation against.

Regards

Ross

[Aemj]

Hi Ross,

Thanks a lot for your kindly explanation.

After reading your answers, the customer’s understanding is as below.

Could you tell me whether the understanding is correct?

As for 1;

The voltage value stated in the comment columns for LDO enabled mode is minimum set point. For example, 1.250V is the minimum set point for operation up to 996 MHz.

As for 2;

PU LDO can be set to 0, when no GPU use.

As for 3;

One must follow the following rules.

- ARM_IN and SOC_IN must be at least 125mV greater than their associated _CAP set point.

- VDD_SOC and VDD_PU output voltage must be set to this rule: VDD_ARM - VDD_SOC / VDD_PU < 50mV. (note-4)

As for 4;

The ‘/’ mark does not mean divisor, and it means ‘OR’ so to speak.

As for 5;

The behavior in 600MHz is not tested in NXP’s BSP, then the voltage values for 600MHz are not guaranteed. One should use the setting for 792MHz if more reliability is needed.

In conclusion, the following setting is fine for them.

Does it correct?

Thanks,

Miyamoto

[RossMcLuckie]

Hi Miyamoto,

All understandings are correct and the table settings is good.

Regards

Ross