Query Regarding Pad Configuration for ENET1 Reference Clock on i.MX6ULL Custom Board

[Embedded-world]

Dear NXP Experts,

I am currently working on a custom board based on the i.MX6ULL processor, and I have a query regarding the pad configuration of the ENET1 interface.

In the reference Device Tree source (DTS) file, the following line configures the Ethernet reference clock:

MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001B031
I would like to understand:

How to correctly interpret and assign this value (0x4001B031) for pad configuration?

Whether this exact configuration can be achieved using the NXP Config Tools, and if so, how?

If not directly supported by the tool, what is the recommended way to apply this configuration manually?

Any guidance or documentation references for properly assigning such pad control values would be greatly appreciated.

Thank you for your support.

Best Regards,
Ravikumar

[Manuel_Salas · Accepted solution]

Hello, @Embedded-world 

I hope you are doing very well.

Sure, the value is to configure the register SW_PAD_CTL_PAD_ENET1_TX_CLK SW PAD Control Register (IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK

You can check this information on reference manual.

So, the final configuration:

HYS = 0: Hysteresis disabled

PUS = 01: 100K Ohm pull-down

PUE = 1: Pull enabled

PKE = 0: Keeper disabled (possibly overridden by PUE)

ODE = 1: Open drain enabled

SPEED = 10: Medium speed

DSE = 0: Low drive strength

SRE = 1: Slow slew rate

Best regards,

Salas.