Provisions of the Round trip time from DDR3 read access time of i.MX6

[takashitakahash]

Dear community.

How much or there are has like a "Round trip time" provisions of read access time of i.MX6, between  output of  theCK from iMX6 to input of DQS from DDR3 memory ?

There are provisions, for example, delays in wiring length iMX6 CK issued must receive 1 / 2 CK during?

If RALAT set to 0, please let me know.

[igorpadykov · Accepted solution]

Hi Takashi

sampling of the incoming DQS (delay) can be changed from the

default ¼ cycle to any value in the range of 0 through 1/2 cycle.

This process is known as the read calibration and described in

AN4467 i.MX 6 Series DDR Calibration, sect.13 "Read DQS Delay

Calibration".

Best regards

igor

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