Problems with Dual-Channel LPDDR2 on i.MX6Q and U-Boot

[steffendoster]

Hi,

I have problems getting a dual-channel LPDDR2 (2x512MB) configuration to work with i.MX6Q.

The board is currently running and works fine except that I only have access to half of the RAM (512MB).

I added my U-Boot cfg-file to this question.

I've set the BOOT_CFG3[5..4] to 01.

U-Boot is 2015-01

Some U-Boot definitions:

#define PHYS_SDRAM                             MMDC0_ARB_BASE_ADDR
#define PHYS_SDRAM_SIZE                   (1024u * 1024 * 1024)
#define CONFIG_NR_DRAM_BANKS      2
#define CONFIG_SYS_SDRAM_BASE     PHYS_SDRAM

Can you help me? 

What other information do you need?

[steffendoster]

Well, OK, I did it in the Past:

Problems configuring 2-Channel LPDDR2 on i.MX6Q 

but I've done the same now and my U-Boot now crashes after "DRAM:  1 GiB".

So OK, the DCD seems to be (mostly) right. And at least U-Boot now says, it has a 1GB RAM (not sure).

There must be another screw to be tweaket before the thing is running. 

Any Ideas?

[Yuri]

Hello,

    I think it makes sense to apply the interleaved mode, since the fixed mode 

cannot guarantee continuous  memory for 512MB chip:

MMDC1 uses addresses from 0x1000_0000 till (0x3000_0000-1) 

MMDC0 uses addresses from 0x8000_0000 till (0xA000_0000-1) 

Regards,

Yuri.

[steffendoster]

Hi, my setting for BOOT_CFG3[5:4] is now 10.

The DCD seems to be (mostly) correct now. But the Bootloader got stuck after "DRAM:  1 GiB".

It seems that it wants to access a part of the RAM (Addresses) which are not available.

[Yuri]

Hi,

  is it possible to check roughly memory with JTAG?

Regards,

Yuri.

[steffendoster · Accepted solution]

I GOT IT WORKING!!!!!!! WHOOOOOOOOOOO!!!!

Turns out, the settings for CS0END were incorrect.

The settings from script-aid were:

Chan0 CS0_END: 0x0000004F

Chan1 CS0_END: 0x00000017

The actually working settings are:

Chan0 CS0_END: 0x00000053

Chan1 CS0_END: 0x00000013

See complete U-Boot cfg for details.

[Yuri]

Hello,

  In the interleaved mode full memory size should be taken for CS0_END calculation.

Regards,

Yuri.

[steffendoster]

Do you want to make sure the RAM is not defect?

In this case it would be far easier to check it with another board.

I simply do not really know how to do this.

The Board worked fine in Single-Channel configuration

[Yuri]

Hello,

  What is BOOT_CFG3[5:4] (DDR Memory Map) in the case?

00 - Single DDR channel

01 - Fixed 2x32 map

10 - 4KB Interleaving Enabled

 Different settings for CS0_END are used for the Fixed and Interleaving modes. 

Look at table in section 2.3 (DDR mapping to MMDC controller ports) and section
44.12.15 (MMDC Core Address Space Partition Register) (MMDCx_MDASP)

of i.MX6 D/Q RM (Rev. 4, 09/2017).

 For the case 01 (Fixed 2x32 map) it is needed to configured both MMDC0 (CS0, CS1)

 and MMDC1 (CS0, CS1) separately.

Also:

i.MX6DL LPDDR2 Support for L3.0.35_4.0.0 

Regards,

Yuri.

[Yuri]

Hello,

  Please provide i.MX6 LPDDR2 connection scheme.

You may create request \ ticket for it.

Support|NXP 

Have a great day,

Yuri

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