Problems configuring LPDDR3 SDRAM for i.MX7ULP

[HenrikZ]

I have a custom board with an i.MX7ULP and a Micron MT52L256M32D1PF LPDDR3 chip that causes some troubles to configure and get working. The Micron ship has the following architecture:

• Density per package: 256 Meg x 32 = 8Gb
• Die per package: 1
• Ranks (Cs_n) per channel: 1
• Configuration per rank (CS_n) 32 Meg x 32 x 8 banks
• Row addressing: 32K A[14:0]
• Column addressing: 1K A[9:0]

It is worth noting that the Micron ship only have on chip select (CS0) which is a different compared to the nanya chip used on the iMX7ULP-EVK.

I have looked into the imximage.cfg to configure the chip and also used the "i.MX7ULP Register programming Aids" to get the configuration correct, however something is missing in my configuration. If I enter the information from the chip above into the excel sheet and enter the settings into the imximage.cfg, there seems to be some issues with the configuration afterwards.
The CPU boots up and I able to enter u-boot. If I then try to run a memtest I get the following:

=> mtest 0x60000000 0x600FFFFC 0xdeadbeef 3
Testing 60000000 ... 600ffffc:
Pattern DEADBEEF  Writing...  Reading...Iteration:      3
Mem error @ 0x600250A0: found DEAE5397, expected DEAE5317
Mem error @ 0x600250A4: found DEAE5398, expected DEAE5318
Mem error @ 0x600250A8: found DEAE5399, expected DEAE5319
Mem error @ 0x600250AC: found DEAE539A, expected DEAE531A
Mem error @ 0x600250B0: found DEAE539B, expected DEAE531B
Mem error @ 0x600250B4: found DEAE539C, expected DEAE531C
Mem error @ 0x600250B8: found DEAE539D, expected DEAE531D
Mem error @ 0x600250BC: found DEAE539E, expected DEAE531E
Mem error @ 0x600252A0: found EAAAEB9E, expected DEAE5397
Mem error @ 0x600252A4: found EEAAEAA8, expected DEAE5398
Mem error @ 0x600252A8: found BAAECA88, expected DEAE5399
Mem error @ 0x600252AC: found AEAA8A9A, expected DEAE539A
... Continues

A few things looks a bit strange, because the pattern that should be written is not correct, and also changes for each memory location. Further what is found is not the same as expected and seems to change with an offset, e.g. the first three lines
DEAE5397 -> DEAE5317
DEAE5398 -> DEAE5318
DEAE5399 -> DEAE5319

It seems that there are some communication to and from the SDRAM, however some settings seems to be wrong, but which settings can cause an error like this?

[JorgeCas]

Hello,

Did you pass the DDR stress test in your board?

When there are changes in expected data/addresses could be caused by timing or signal integrity issues.

Best regards.

[HenrikZ]

Hi

Thanks for you suggestion. I tried to run the calibration and afterwards the DDR stress test. Even though the both were successful, I still get errors when running the mtest from u-boot. I haven't copied the result, since they are identical to the first time I ran the test.
More suggestion where to look for wrong configurations will be highly appreciated

Below are the results from the calibration test. 

Best regards
Henrik

// READ DQS DELAY:
setmem /32 0x40AB0848 = 0x5C5C5C5C // MPRDDLCTL PHY0
// WRITE DQS DELAY:
setmem /32 0x40AB0850 = 0x1A1A1A18 // MPWRDLCTL PHY0

... and the stress test:

============================================
        Chip ID
CHIP ID = i.MX7 UltraLitePlus(0x73)
============================================

ARM Clock FIX to 500MHz

============================================
        DDR configuration
DDR type is LPDDR3 in 1-channel mode.
Data width: 32, bank num: 8
Row size: 15, col size: 10
Chip select CSD0 is used 
Density per chip select: 1024MB 
Density per channel: 1024MB 
============================================
DDR Stress Test Iteration 1
DDR Freq: 316 MHz
t0.1: data is addr test
t0: memcpy11 SSN test
t1: memcpy8 SSN test
t2: byte-wise SSN test
t3: memcpy11 random pattern test
t4: IRAM_to_DDRv2 test
t5: IRAM_to_DDRv1 test
t6: read noise walking ones and zeros test
Success: DDR Stress test completed!!!​

[JorgeCas]

Hello,

Is your board able to detect the correct amount of memory in U-boot log?

Best regards.