Hi Victorien,
I am using your clock correction patch for a while and I noticed a mistake when setting the SAIF clock in mxs_saif_set_clk(). Setting the clock rate with clk_set_rate(master_saif->clk, round_mclk); only works if the master clock is 384*fs or 512*fs. For example I have a codec which does only support 192*fs for sample rates of 192kHz. Therefore, the desired master clock is 36.864MHz. Now, using your patch the wrong clock divider is set to HW_CLKCTRL_SAIF0_DIV (0x13A9 instead of 0x2752).
Note, that a comment in the mainline driver notes: SAIF clock should be either 384*fs or 512*fs. Therefore, I fixed the issue by setting clk_set_rate(master_saif->clk, [384|512]*fs); depending on the sampling rate.