Here's some updates:
I changed pin groups, added a 5th led that is re-mapped from backlight PWM (for experiment, because this pin is easily accessible for masurements)
Here's the patch.
The original file can be found at:
linux-2.6-imx/imx6qdl-var-dart.dtsi at imx_3.14.28-r0_var3 · varigit/linux-2.6-imx · GitHub
GPIO4_27, 4_28, 4_30 all work, 6_20 and 6_21 still don't.
Could this be a power-domain issue? Because the board I have uses RGMII ethernet PHY and GPIO6_20 and GPIO6_21 are DDR balls and used to be NVCC_RGMII power domain.
Do I need to change them to NVCC_GPIO power domain if I want to use those pins as GPIO?
--- imx6qdl-var-dart.dtsi 2015-12-28 12:01:02.450450949 -0500
+++ imx6qdl-var-dart1.dtsi 2015-12-31 14:13:00.591197693 -0500
@@ -197,14 +197,43 @@
status = "okay";
};
#endif
- backlight {
- compatible = "pwm-backlight";
- pwms = <&pwm2 0 50000>;
- brightness-levels = <0 4 8 16 32 64 128 248>;
- default-brightness-level = <7>;
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-0 = <&pinctrl_leds>;
status = "okay";
- };
-
+ led@0 {
+ label = "carrier0";
+ gpios = <&gpio4 27 0>;
+ linux,default-trigger = "default-on";
+ default-state = "on";
+ };
+ led@1 {
+ label = "back_light";
+ gpios = <&gpio6 21 0>;
+ linux,default-trigger = "default-on";
+ default-state = "off";
+ };
+ led@2 {
+ label = "lcd_en";
+ gpios = <&gpio6 20 0>;
+ linux,default-trigger = "default-on";
+ default-state = "off";
+ };
+
+ led@3 {
+ label = "carrier1";
+ gpios = <&gpio4 28 0>;
+ linux,default-trigger = "default-on";
+ default-state = "on";
+ };
+ led@4 {
+ label = "j17_2";
+ gpios = <&gpio4 30 0>;
+ linux,default-trigger = "default-on";
+ default-state = "on";
+ };
+ };
+
v4l2_cap_0 {
compatible = "fsl,imx6q-v4l2-capture";
ipu_id = <0>;
@@ -253,16 +282,6 @@
soc-supply = <&sw1c_reg>;
};
-
-&fec {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_enet_4>;
- phy-mode = "rgmii";
- phy-reset-gpios = <&gpio1 25 0>;
- fsl,magic-packet;
- status = "okay";
-};
-
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
@@ -369,7 +388,7 @@
/* PMIC INT */
MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000
/* Wifi Slow Clock */
- MX6QDL_PAD_ENET_RXD0__OSC32K_32K_OUT 0x000b0 /* WIFI Slow clock */
+ // MX6QDL_PAD_ENET_RXD0__OSC32K_32K_OUT 0x000b0 /* WIFI Slow clock */
/* Audio Clock */
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* Audio Codec Clock */
/* Camera Clock */
@@ -388,39 +407,13 @@
MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
>;
};
-
- pinctrl_enet_4: enetgrp {
- fsl,pins = <
- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
- >;
- };
-
- pinctrl_enet_irq: enetirqgrp {
- fsl,pins = <
- MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
- >;
- };
-
+#if 0
pinctrl_gpio_keys: gpio_keysgrp {
fsl,pins = <
// MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x80000000
>;
};
-
+#endif
pinctrl_hdmi_cec: hdmicecgrp {
fsl,pins = <
MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
@@ -455,37 +448,13 @@
>;
};
- pinctrl_ipu1: ipu1grp {
+ pinctrl_leds: ledgrp {
fsl,pins = <
- MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
- MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
- MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
- MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
- MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x80000000
- MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
- MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
- MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
- MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
- MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
- MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
- MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
- MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
- MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
- MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
- MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
- MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
- MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
- MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
- MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
- MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
- MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
- MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
- MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
- MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
- MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
- MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
- MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
- MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
+ MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x10
+ MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x10
+ MX6QDL_PAD_RGMII_TD0__GPIO6_IO20 0x010
+ MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x010
+ MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x010
>;
};
@@ -506,11 +475,6 @@
>;
};
- pinctrl_pwm1_1: pwm1grp {
- fsl,pins = <
- MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x1b0b1
- >;
- };
/* Linux Console */
pinctrl_uart1_1: uart1grp-1 { /* RX/TX only */
fsl,pins = <
@@ -821,13 +785,6 @@
status = "okay";
};
-
-&pwm2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pwm1_1>;
- status = "okay";
-};
-
&ssi2 {
fsl,mode = "i2s-slave";