Priority of the AXI bus in i.MX7D

[ko-hey]

Hi all

Does anyone have the manual for Quality of service controller (QoSC) ?

My customer want to check the priority of AXI bus for i.MX7D.

Because When using SDMA, the output image of MIPI DSI was distorted.
So I doubt the priority of AXI.

I understand the QoSC control the priority of the AXI bus.

However, there are no explanation about it.

Could you tell me the detail of the QoSC and how to check the priority of the AXI ?

Ko-hey

[art]

There is the NIC-301 Network Inter-Connect AXI arbiter IP by ARM that controls the access priority on the AXI/AHB bus. It is briefly decribeed in the Section 4.6 of the i.MX7Dual Reference Manual document. The detailed documentation is also available from ARM for free:

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0397f/index.html

The access priorities are configured through a set of Global Programmer's View (GPV) areas, refer to the processor's memory map description in the Reference Manual document.

The NIC-301 default settings are configured by the board support package (BSP) software, and in most cases should not be modified by the customer. The default settings have gone through exhaustive testing during the validation of the part,
and have proven to work well for the part's intended target applications. Changes to the default settings may result in a degradation in system performance.

You can try to check the BSP code that sets up NIC-301 on your own risk.

Have a great day,
Artur

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[ko-hey]

Hi art‌

I looked at the link that you answered but please teach me the specific setting place.

I understand the following things.
· AXI bus priority can be set with NIC-301
· NIC-301 can be set by GPV
· The default setting of NIC-301 is set by BSP software

Based on the above, here is a question

Q1

I checked the Linux code, but I could not find the part setting the NV GPV.

Please tell me the code location you are setting.

with iMX6 code, the priority of QoS is set with the register of IOMUXC_GPR6.

We also found changes in the Linux code mach - imx 6q.c. A similar part was not found in mach - imx7d.c.

Q2

What is the register location to set the bus priority in the setting in the AXI?

I read through the document , but I could not find the corresponding setting part.

Q3

There was a register map of the GPV setting register in the received material as follow.

But I do not know the details of internal setting. Please tell me the details below.

Master interface 0 - n,

Slave Interface 0 - m,

Internal Interface 0 - p, 

Which peripheral do support in iMX7?

EX)

Can you provide information such as correspondence with Master interface 0 = LCDIF?

Ko-hey

[ko-hey]

Hi art‌

Could you understand my question ?

If yes, please answer.

Ko-hey

[ko-hey]

Could someone answer this question ?

Ko-hey

[ko-hey · Accepted solution]

Hi all 

I got answer from R&D team in other thread.

As a result, user can not modify the NIC-301 priority.

Here is a answer:

The QOS details are set at chip design time. The notes were mistakenly put in the reference manual and are intended for the chip designer, not the chip user. The "NIC-specific parameters" are not published for the chip user.
NXP does not expect customer's to program this module based on the note in the reference manual. The BSP uses the design time settings and does not modify the NIC-301 at all.

The reference manual will be updated to remove the contents after this note.

Ko-hey