Powering SD3 port with NVCC_LOW

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Powering SD3 port with NVCC_LOW

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ambroisealgrin
Contributor II

Hi,

I'm working on a custom board based on an iMX6 solo X (ref.: MCIMX6X1CVO08AB).

On the SD3 port, i have a WL1805 module which works in 1V8. The SD3 port is powered by NVCC_HIGH(3V1 on my board) and NVCC_LOW (1V8).

I am booting from an eMMC on SD4 port from fuse. In Table 5-6. MMC/eMMC Boot Fusemap,BOOT_CFG2[1] is use for setting SD3 voltage. Is BOOT_CFG2[1] worked only when booting from SD3, or it could be use in my case for setting the SD3 port power when booting from SD4 ?

If not, how can i set SD3 power to NVCC_LOW in linux ?

Thanks for your help,

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi ambroisealgrin

BOOT_CFG2[1] works also when booting from SD4,

in linux one can set LVE bit in IPOMUX pad register

Best regards

igor

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ambroisealgrin
Contributor II

Hi igorpadykov,

Thanks for your answer. As you said, i set the fuse to 1, i had a level of 2.2V on my IOs, which lokk like a conflict between the external 1V8 Pull up and the iMx voltage.

So i set LVE bit and i still have this conflict.

Did i make something wrong ?

Fuse read in uboot is :

Normal Boot

Hit any key to stop autoboot:  0

=> fuse read 0 5

Reading bank 0:

Word 0x00000005: 00005a61

DTS configuration

&usdhc3 {

    pinctrl-names = "default";

    pinctrl-0 = <&pinctrl_usdhc3>;

    bus-width = <4>;

    cap-power-off-card;

    keep-power-in-suspend;

    status = "okay";

    wlcore: wlcore@2 {

        compatible = "ti,wl1805";

        reg = <2>;

    };

};

pinctrl_usdhc3: usdhc3grp {

            fsl,pins = <

                MX6SX_PAD_SD3_CMD__USDHC3_CMD        0x417059

                MX6SX_PAD_SD3_CLK__USDHC3_CLK        0x410059

                MX6SX_PAD_SD3_DATA0__USDHC3_DATA0    0x417059

                MX6SX_PAD_SD3_DATA1__USDHC3_DATA1    0x417059

                MX6SX_PAD_SD3_DATA2__USDHC3_DATA2    0x417059

                MX6SX_PAD_SD3_DATA3__USDHC3_DATA3    0x417059

                MX6SX_PAD_SD3_DATA4__GPIO7_IO_6     0x41b0b0

                MX6SX_PAD_SD3_DATA5__GPIO7_IO_7     0x41b0b0

            >;

        };

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igorpadykov
NXP TechSupport
NXP TechSupport

could you connect jtag and check if LVE is set ?

~igor

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ambroisealgrin
Contributor II

I have a jlink segger probe, configuration files for imx6sx aren't avalaible on segger website, has freescale got one ?

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igorpadykov
NXP TechSupport
NXP TechSupport

some scripts for j-link can be found on

I.MX6SX SoloX Debugging

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ambroisealgrin
Contributor II

Hi igorpadykov,

Sorry for the long time to answer, i checked the register and the LVE bit was unset.

I tried a new approach by setting the port in 1V8 in uboot.

The LVE option wasn't avalaible for imx6sx, in a first time i just had "(1 << 22)" in the iomux_v3_cfg_t. Didn't work.

So i did some change iomux-v3.c/.h and now adding PAD_CTL_LVE in the struct iomux_v3_cfg_t make SD3 pads working in 1V8 in uboot (see attached file).

I think it should be a similar problem for the linux part.

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