Power-up sequence of DDR and NVCC supply

[vijayalakshmi]

Can the DDR supply be applied after the NVCC_xxxx supplies have been applied for i.mx6 SoloDualLite device.

[art]

Do you mean the i.MX6 Solo or DualLite processors? If so, the i.MX6Solo/DualLite Data Sheet document does not define any special sequencing of NVCC_DRAM supply voltage versus other NVCC_xxxx voltages. So, the answer is: yes, it is possible to apply NVCC_DRAM voltage after other NVCC_xxxx voltages on i.MX6Solo/DualLite processors.

Have a great day,
Artur

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[vijayalakshmi]

Thank you for the reply.

We are using a Dual Lite part. We had this doubt as in the reference Schematic SCH-27767, NVCC_xxxx are applied after all other supplies are applied (i.e P3V3_DELAYED which is controlled by VGEN5 of PMIC).

[weidong_sun · Accepted solution]

Hello,

       i.mx6 SoloDualLite ? we don't have this type of processor, maybe it is i.MX6SL(Sololite)

       You can refer to i.MX6SL evk schematic(spf-27452_b.pdf), see page 4, from it, you can find SW3/SW4 supply DDR, it also means DDR's power should be up after SW1(VDD_ARM_IN / VDD_SOC_IN) & SW2(VDD_HIGN_IN1/2/3/4).

Regards,

weidong