Parameter constraints for i.MX6 spread-spectrum clocking?

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Parameter constraints for i.MX6 spread-spectrum clocking?

928 Views
MOW
Contributor IV

Dear i.MX-Community

We're using i.MX6-SoCs (Solo, DualLite, Dual, Quad, and QuadPlus) on several different custom board designs. We're using the spread-spectrum feature of the 528 MHz "system PLL" and didn't have any issues with these, so far. For a new board-design we needed somewhat "more aggressive" spreac-spectrum settings, so we started testing with several different parameters, during which we noticed strange behavior: a different parameter-set from our default settings, which should result in the same frequency-settings, results in a very unstable system (segmentation faults, exceptions, corrupted data reads from memory, etc. under Yocto-Linux with 4.1.15 kernel).

To be more specific (on an i.MX6D):

  • PLL_SYS_SS[STOP] = 250, PLL_SYS_SS[STEP] = 1, PLL_SYS_DENOM[B] = 400 works fine without any problems on all devices.
  • PLL_SYS_SS[STOP] = 500, PLL_SYS_SS[STEP] = 2, PLL_SYS_DENOM[B] = 800 on some devices results in the Linux kernel crashing sooner or later (sometimes already during the boot-process, sometimes after a couple of minutes) on almost every boot. Some few identically equipped devices don't seem to have problems with these settings, though.
  • (PLL_SYS_NUM[A] is set to the default value of 0 in either case)

Either setting should result in the same spread spectrum range of 15 MHz and modulation frequency of 48 KHz and verification with an oscilloscope by configuring the CLKO2-output to "mmdc_ch0_clk_root/7" shows that the clock seems to be behaving as expected.

Are there any constraints on valid combinations of parameters, that should be followed for the spread-spectrum settings? I can't seem to find any constraints being mentioned in the reference manual, datasheet or application notes.

Kind regards,

Marc

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3 Replies

190 Views
igorpadykov
NXP TechSupport
NXP TechSupport

Hi Marc

recommended ddr dithering range is about 1%, for i.MX6 there are no special

restrictions for combinations of parameters. If some modules use that clock,

it is necessary to consider how dithering clock may affect them.

Best regards
igor
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190 Views
MOW
Contributor IV

Hi Igor

If there are no restrictions for combinations of parameters, how come that one set of parameters works fine, while the other - resulting in the same final modulation effects - does not work stable at all on the same board?

According to the formulas given in the reference manual (and oscilloscope measurements), both parameter sets result in 

  • a spread spectrum range of 15 MHz
  • a modulation frequency of 48 KHz
  • and a frequency change step of 60 KHz

But we have boards on which one parameter set works fine, while the other set doesn't work at all. So what can be the difference?

Kind regards,

Marc

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190 Views
igorpadykov
NXP TechSupport
NXP TechSupport

Hi Marc

please try to analyze issue observing mmdc signal on clko pin using CCM_CCOSR register.

Please also try with baremetal tests, to exclude opearting system side effects:

Github SDK
https://github.com/backenklee/swp-report/tree/master/iMX6_Platform_SDK

Best regards
igor

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