Parallel to mipi-csi2 issue for toshiba chip TC358748

[deshenggao]

Hi  all:

  We  use a  toshiba chip TC358748 to  convert  the Parallel  RGB888   Signal  to MIPI -CSI2 .

(RGB888, NTSC,480P,  clock  162MHz,  data 0/1 enable)

With the same setting , the  i.MX6  can work well with  the  ADV7480 ( HDMI to mipi-csi 2 device,(RGB888, NTSC,480P,  clock  162MHz,  data 0/1 enable)

but , can not capture the data of the TC358748.  We can see that the clock and data line have  the correct data.

and it is almost same with the ADV7480,  but we can not receive the data.

What should we check?

Thank you!

[hok]

Hey Desheng!

I'm also in this situation to implement a parallel camera with RGB888 to CSI-2. May is it possible that you can offer me the configuration for TC358748 and which camera you are using...

I would be also very happy if you are able to share a patch set with implementation...

Thanks in advance

Horst

[leenighteif]

Hi,can you tell me how to solve the problem ?Thank you  !

[deshenggao · Accepted solution]

Hi:

  We found the reason .Thank you!

[smusserRosen]

Hi there,

Would you mind elaborating on your solution? What was the reason transmission was failing with the TC48 chip?

Thanks!

[deshenggao]

Hi 

I have a  new update informaiton that the  TC358748 is not support the  Line Start Code.

The Line Start Code is  necessary  for    i.MX6?

If  so , I think  it means that  TC358748 can not work with  i.MX6?

or we have other ways to solute this issue.

thank you

[deshenggao]

We  have checked that

the  register  MIPI_CSI_PHY_STATE bits 8 and 9  will toggle from 0x300 to 0x330.

and  the registers MIPI_CSI_ERR1 and 2. They are  0x00.

[deshenggao]

Hi  igor:

   Thank you,

I found that the signal between TC358748  and ADV7480 ,  there are some difference.

The ADV7480  is the HVALID  synchronization signal ,(please see the  IMX6DQRM   Figure 40-10 )

But the TC358748  is the  VVALID synchronization signal.,(please see the IMX6DQRM   Figure 40-11 )

I try to change  the    Non-gated Clock mode to  Gated  clock mode.

but it is not worked.

What  different setting should be done for these two signals?

What  register  would be different  between these two  different  signal types?

Thank you 

[deshenggao]

I upload the data line signal  of  ADV7480  and  TC358748.

the  data line signal of  ADV7480 (ch2 is  D+,   CH3 is D-)

this picture is  the Hsync end and start

the  data line signal of  ADV7480 (ch2 is  D+,   CH3 is D-)

in this picture , you will see the  vsync

below is the  data signal of  TC358748 (ch2 is  D+,   CH3 is D-)

You will see that there are some difference  between  them

below is the  data signal of  TC358748 (ch2 is  D+,   CH3 is D-)

About the Vsync  see that there are some difference  between  them

Does the i.MX6  should made different setting for these signal?

Please kindly check

Thank you!

[deshenggao]

Hi

about the  HVALID  synchronization signal  and the  VVALID synchronization, maybe I have a misunderstanding.

If wrong,

Pleae  ignore  these information.

I have upload the  data line signal picture about the   ADV7480  and  TC358748 above.

Current setting can work with   ADV7480   ,but can not work with    TC358748.

Please give me some advices to setting the register or the capture parameter.

Thank you !

[igorpadykov]

Hi Desheng

please try to follow steps given in Debug steps for customer MIPI sensor.docx

and set correct clock frequency

https://community.freescale.com/docs/DOC-94312

So for example in ov5640_mipi case (2 data lanes are used)

MIPI_CSI_PHY_STATE bits 8 and 9 must be 1 (0x300) and bits 4~7 will

toggle according to the moment you read the register and the state of the transmission.

In case of sabresd, as it uses only 2 lanes, this register will toggle from 0x300 to 0x330.

Check the registers MIPI_CSI_ERR1 and 2. They must be 0x00.

It may be useful to check

i.MX6Q MIPI CSI2: Capturing RAW12 generic data | NXP Community

Best regards

igor

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