Parallel-mode CSI0 without SYNC signals?

[olegpereverzev]

Good time of the day, we are developing a device, that implies using CSI0 as fast input of raw data. The source of data (FPGA) generates only data + clock signal.

And this is the problem - as i understand CSI0 needs at least VSYNC or special-formed BT.656/BT.1120 signal, but FPGA has none of that.

Can CSI0 work without VSYNC? (And If i connect it to high level in hardware?) Or i should try adding another little FPGA so it would for example count up to 255 on PIXCLK and generate VSYNC on 8-bit buffer overflow?

It is not good solution, as it increases complexity and price of overall device. Goal is just to receive data from CSI0 pins and save it to memory, no other hardware processing.

Thanks in advance.

[igorpadykov]

Hi Oleg

unfortunately CSI0 can work without VSYNC or

embedded BT.656/BT.1120 syncs.

Best regards

igor

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[olegpereverzev]

Thanks Igor! Is there some time limits between last byte of packet (last pixelclk impulse) and vsync signalizing next "frame"? Can i just send stable e.g. 60MHz signal and simply pass vsync each fixed n-th byte transmitted? Like in without delays between each "frame"?