Parallel RGB Displays

[rajniks]

On IMX6 processors how are IPU DATA lines assigned to Red, Blue and Green color lines. I can't seem to find out from reference manual and other documents. I also need to know how should I provide the connections so that both 18bit as well as 24 bit parallel RGB displays can be interfaced.

[Yuri]

Display (color bit mapping is software configurable. When configuring display output pins,

the following should be taken into account.

1.

General scheme is shown on Figure 37-32 (Mapping scheme) of the i.MX6DQRM.

2.

From Table 37-25 (DC template's fields description) :

«The MAPPING field holds a pointer to a register holding 3 fields: MAPPING_PNTR_BYTE0_X,

MAPPING_PNTR_BYTE1_X, MAPPING_PNTR_BYTE2_X. This pointers point to sets of OFFSET and

MASK parameters that define the mapping scheme. MAPPING =0 means that mapping is disabled.»

3.

Section 37.4.7.5.1 (Bus Mapping Unit) describes the mapping feature in more details.

On the Figure 37-32 (Mapping scheme), microcode field MAPPING = 2.

That is, register IPUx_DC_MAP_CONF_1 should be used for configuring; please refer to section 37.5.336

[DC Mapping Configuration Register 1 (IPUx_DC_MAP_CONF_1)] of the Reference Manual.

As an example let we set :

MAPPING_PNTR_BYTE2_2 = 2

MAPPING_PNTR_BYTE1_2 = 1

MAPPING_PNTR_BYTE0_2 = 0

then

IPUx_DC_MAP_CONF_15 register should be set as following :

(section 37.5.350 DC Mapping Configuration Register 15 (IPUx_DC_MAP_CONF_15))

MD_OFFSET_1 = 0x0D ; MD_MASK_1 = 0xFC

MD_OFFSET_0 = 0x05 ; MD_MASK_0 = 0xFC

IPUx_DC_MAP_CONF_16 :

MD_OFFSET_2 = 0x16 ; MD_MASK_2 = 0xFC

4.

Please refer to  Chapter 18 (Configuring the IPU Driver) of "iMX6_Firmware_Guide.pdf" in the Platform SDK.

https://www.freescale.com/webapp/Download?colCode=i.MX6_PLATFORM_SDK&location=null

http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=i.MX6Q&fpsp=1&tab=Design_Tools_Tab

5.

  Please use i.MX6 Datasheet(s) to define typical IPU display output formats.

For example please take a look at section 4.11.10.4 (IPU Display Interface

Signal Mapping) of IMX6SDLCEC (Rev. 2.1, 05/2013).

Have a great day,
Yuri

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[shefft]

2

Hi Yuri,

i'm a little confused by this.  The SDK uses a MAPPING=2 as in your example in the post here

microcode.mapping = 2;

//select map conf 2

in ipu_dc.c

but then they use either MAPPING_PNTR_BYTEX_0 or MAPPING_PNTR_BYTEX_1 (depending on another value, which I don't understand the source of) which are both in IPU_DC_MAP_CONF_0 and not IPU_DC_MAP_CONF_1 as you indicate.

ipu_write_field(ipu_index, IPU_DC_MAP_CONF_0__MAPPING_PNTR_BYTE2_0, 2);

ipu_write_field(ipu_index, IPU_DC_MAP_CONF_0__MAPPING_PNTR_BYTE1_0, 1);

ipu_write_field(ipu_index, IPU_DC_MAP_CONF_0__MAPPING_PNTR_BYTE0_0, 0);

or

	ipu_write_field(ipu_index, IPU_DC_MAP_CONF_0__MAPPING_PNTR_BYTE2_1, 6);
	ipu_write_field(ipu_index, IPU_DC_MAP_CONF_0__MAPPING_PNTR_BYTE1_1, 5);
	ipu_write_field(ipu_index, IPU_DC_MAP_CONF_0__MAPPING_PNTR_BYTE0_1, 4);

To add to the confusion, the reference manual seems contradictory:

"The MAPPING field holds a pointer to a register holding 3 fields: MAPPING_PNTR_BYTE0_X,

MAPPING_PNTR_BYTE1_X, MAPPING_PNTR_BYTE2_X.

This pointers point to sets of OFFSET and MASK parameters that define the mapping scheme. MAPPING =

0 means that mapping is disabled.

The value in this field should be incremented by 1 to get the correct X pointer value

In order to point to MAPPING_PNTR_BYTE2_0, MAPPING_PNTR_BYTE1_0, MAPPING_PNTR_BYTE0_0

the user should write 1 to the MAPPING field"

Incrementing 1 gives me 2, not 0.

So which is it?  If the MAPPING=2, is it pointing to MAPPING_PNTR_BYTEX_3, MAPPING_PNTR_BYTEX_2, MAPPING_PNTR_BYTEX_1, or MAPPING_PNTR_BYTEX_0?

BTW, I'm on an i.mx6SDL

[qiang_li-mpu_se]

You can reference to attached sample code.

DC MAPPING=2 (Mapping pointer #1 in reference manul) is fixed in PNTR_BYTE0_1, PNTR_BYTE1_1, PNTR_BYTE2_1. But MD_OFFSET_<i> and MD_MASK_<i> can be any of the valid value.

For Mapping pointer #1, the value setting in microcode_config should be 2 " incremented by 1".

[Yuri]

  The SDK test codes for IPU look as contradicting to the Reference Manual,

in the same time, I tried to run the SDK IPU test  - it is working.  Hope Qiang_FSL
helps to clarify the issue.

~Yuri

[rajniks]

Thanks Yuri for the detailed explanation. Many times you get lost in the huge reference manual of IMX6. I found IPU Display Interface Signal Mapping (4.11.10.4) in the datasheet of IMX6DQ like the  one you had shared for . I will use the same as given in the table for 18 bit RGB as well 24 bit RGB.