Our iMX6 board uses the quad-core and the PMIC0100. The CPU sends out the PWRON Signal to the PMIC, when it is ready to start-up.The data sheet says tha there is a typical delay of 1ms - user determined delay. But our PWRON Signal is practically identical with the VSNVS voltage. Did I miss something here?
Sorry for the delay in responding.
Well, you just refer to the data sheet, but this doesn't correlate with what I observe on my board. Further, the data sheet mentiones a typical user determined delay of 1ms: How can I manipulate this user determined delay? External delay gate or RC filter? All the reference designs do not show any additional circuitry - so where is this 1ms coming from?
Sorry I didn't explain. As you can see in table 11, the timing between VSNVS and PWRON is defined by the user. PWRON is actually an input to the PF0100, so this timing depends on what you have externally connected to both VSNVS and PWRON, but it doesn't mean you need 1ms for the device to work properly.
Please see figure 6 and table 11 of the PF0100 datasheet located here:
They explain the behavior of VSNVS startup. Plesae let me know if you have more questions.