PN7160 opcode error

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PN7160 opcode error

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ram-nimmala
Contributor II

I am integrating nfc module PN7160 for iMX8 platform using the android integration guide AN13189.

While testing i can see the below logs from the logcat. because of this i am not able to test nfc card.

 

complete log is attached with this

Please let me know if there is a problem here.

6:56:54.970 564 644 I notification_panel_hidden:
07-26 16:56:56.288 409 1477 D NxpNciR : len = 3 > 612300
07-26 16:56:56.288 409 1477 D NxpTml : PN54X - Posting read message.....
07-26 16:56:56.289 409 1480 D NxpHal : read successful status = 0x0
07-26 16:56:56.289 409 1480 D NfccPowerTracker: NfccPowerTracker::ProcessNtf: Enter
07-26 16:56:56.289 1213 1473 I libnfc_nci: [INFO:nfc_ncif.cc(501)] NFC received ntf gid:1
07-26 16:56:56.289 409 1477 D NxpTml : PN54X - Read requested.....
07-26 16:56:56.289 409 1477 D NxpTml : PN54X - Invoking I2C Read.....
07-26 16:56:56.289 1213 1473 E libnfc_nci: [ERROR:nci_hrcv.cc(305)] unknown opcode:0x23
07-26 16:56:56.782 409 1477 E NxpTml : Read _>>>>> Empty packet recieved !!
07-26 16:56:56.782 409 1477 D NxpTml : PN54X - I2C Read successful.....
07-26 16:56:56.782 409 1477 D NxpNciR : len = 3 > 612100
07-26 16:56:56.782 409 1477 D NxpTml : PN54X - Posting read message.....
07-26 16:56:56.782 409 1480 D NxpHal : read successful status = 0x0
07-26 16:56:56.783 409 1480 D NfccPowerTracker: NfccPowerTracker::ProcessNtf: Enter
07-26 16:56:56.783 409 1477 D NxpTml : PN54X - Read requested.....
07-26 16:56:56.783 409 1477 D NxpTml : PN54X - Invoking I2C Read.....
07-26 16:56:56.783 1213 1473 I libnfc_nci: [INFO:nfc_ncif.cc(501)] NFC received ntf gid:1
07-26 16:56:56.783 1213 1473 E libnfc_nci: [ERROR:nci_hrcv.cc(305)] unknown opcode:0x21

1 Reply

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gfuchs
Contributor I

Hi Ram,

I had the same problem. Opcode 0x21 means PLL could not lock on. That's why tag discovery does not work. I fixed it by configuring the clock source as coming from the crystal. I modified the configuration file vendor/nxp/nfc/hw/pn7160/libnfc-nxp.conf. Change the definition for the clock source NXP_SYS_CLK_SRC_SEL on line 43 from 0x02 (CLK_SRC_PLL) to 0x01 (CLK_SRC_XTAL).

Best wishes,

Günter

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