PLL_AUDIO:DIV_SELECT

[chrisolarti]

When configuring the PLL_AUDIO:DIV_SELECT for achieving 632.217MHz to obtain a Sample Frame Rate of 22.050kHz as per i.MX 6Dual/6Quad Applications Processor Reference Manual, Rev. 3, 07/2015, Table 61-7 SSI Bit Clock....

The main equation is

PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM)

So when replacing values:

632.217MHz = 24MHz * (DIV_SELECT + NUM/DENOM)

26.342 = DIV_SELECT + NUM/DENOM

DIV_SELECT = 26

NUM = 342

DEOM = 1000

However when looking at Table: CCM_ANALOG_PLL_AUDIOn field descriptions, DIV_SELECT has a valid range from 27-54.

So the question is: Should the comment for DIV_SELECT change from 27-54 to 26-54?  We are currently using 26, and that is working for us, but we need to make sure we are within the iMX6 limitations.  If 27 is enforced, then can you please help us to configure the proper values for trying to achieve a 22.050 kHz sample rate.

Thanks in advance.

Chris Olarti.

[igorpadykov]

Hi Chris

please try double settings:
2*632.217MHz = 24MHz * (2*DIV_SELECT + 2*NUM/DENOM)
2*26.342 = DIV_SELECT + NUM/DENOM
DIV_SELECT = 26*2
NUM =2*342
DEOM = 1000

with appropriate divider in ssi_clk_pred,ssi_clk_podf in CCM_CSnCDR
in Table 61-7 (doubling SSIDIV in CCM)

from sect.18.5.1.3.4 Audio / Video PLL  i.MX6DQ RM:

The clock output frequency range for this PLL is from 650 MHz to 1.3GHz.

http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6DQRM.pdf 

Best regards
igor
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