PF0200 Turn off event

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PF0200 Turn off event

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daveebright
Contributor III

In the MMPF0200 datasheet section 6.4.2.2 Turn Off Events item 2 it says:

2. PWRON_CFG bit =1, SWxOMODE bit = 0, PWRONRSTEN = 1 and PWRON is held low for longer than 4.0 seconds.

    Alternatively, the system can be configured to restart automatically by setting the RESTARTEN bit.

If possible I'd like to test this using the SABRE Board with the i.MX6 SoloX (which I have).  That is I'd like to reconfigure the PF0200 registers so that when the reset button is held down for longer than 4 seconds it powers off and then automatically restarts.  I'm pretty sure I can modify the pfuze100 regulator driver to reconfigure the PWRCTL register to set PWRONBDBNC, PWRONRSTEN, and RESTARTEN appropriately, but I'm not sure about PWRON_CFG and SWxOMODE.  Since SWxOMODE defaults to 0, I think these do not need to be set.  So that leaves PWRON_CFG which I believe is defaulted to 0 and I want it to be 1.

First off I am not sure if this can be done since these registers are in the OTP section (0xE0, 0xE1, and 0xE2).  Although it mentions these are OTP redundant bits which can be XOR'ed to allow the function to be changed multiple times.  I also do not understand from reading the documentation how that is done.  There is PWRON_CFG1,2, and 3 as well as PWRON_CFG_XOR (0xE3), but using this how do you select which configuration is used?  What PWRON_CFG bit do I need to set to 1?

Any help understanding if this even possible on the SABRE board and more details on how to do it would be appreciated.  Even if it cannot be done on the SABRE board, I'd like to understand this because we are building a custom board based on the SABRE board design (can set the fuses in the PMIC before populating it on the board).  Thanks!!!

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reyes
NXP TechSupport
NXP TechSupport

Hi Dave,

We do not have any script or code with this information, but, in order to do this, you will need to set the following configuration:

All PWRON_CFG bit = 1 (as an edge sensitive input),

All SWxOMODE bit = 0 (any regulator whose SWxOMODE bit is set to “0” will be turned off),

RESTARTEN bit = 1 (setting this bit should make an automatic restart after pressing the PWRON button low for more than 4 seconds),

PWRONRSTEN = 1 

PWRON is held low for longer than 4.0 seconds.

This is how this configuration is done:

All PWRON_CFG bit = 1:

                PWRON_CFG1 bit 4 on Register 0xE0 (*Extended Page 1)

PWRON_CFG2 bit 4 on Register 0xE1 (*Extended Page 1)

PWRON_CFG3 bit 4 on Register 0xE2 (*Extended Page 1)

All SWxOMODE bit = 0:

                SW1ABOMODE bit 5 on Register 0x23

SW2OMODE bit 5 on Register 0x38

SW3AOMODE bit 5 on Register 0x3F

SW3BOMODE bit 5 on Register 0x46

PWRONRSTEN = 1:

                PWRONRSTEN bit 1 on Register 0x1B

RESTARTEN = 1:

                RESTARTEN bit 0 on Register 0x1B

Then, PWRON is held low for longer than 4.0 seconds. After that, an automatic restart should occur.

*In order to enter to Extended Page 1, you first need to write 0x01 to the page register at address 0x7F.

Best Regards,

Jose

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daveebright
Contributor III

Jose,

I modified the pfuze100_regulator.c file probe function to perform the operations you described.  However I found out that the updates did not have an immediate impact.  Therefore I added additional code to set the TBB_POR bit (bit 7) in the OTP FUSE POR1 (address 0xE4) register as a last step after setting all the registers you had suggested.  This still did not have any impact until I did a power on event (pushed the reset button on the SABRE board).  Then after the board rebooted, the try-before-buy functionality was in place and the reset button now has the functionality I desired to prototype (hold for button for 4 seconds and then the board automatically reboots).  Note I also added a coincell to the board and turned on the coincell charger (not sure if this is necessary for this to work) since there was mention that it was needed for TBB mode.  I am happy that I can now prototype this functionality.  Thanks!

The reason I wanted this functionality is for a factory default reset button.  There are still a couple problems however.  First there is no interrupt which distinguishes between the button press as the reason for the reset versus another power off/on (watchdog, SW reboot, pull the power, etc.).  In the old mc13892 there was a SYSRSTI generated on the next power up which indicated the button push was the reason for the reset.  Am I missing something?  I need this to signal that a factory reset is to be done during the boot process.

The other issue I am having is due to the SABRE board hardware.  The issue is that besides the reset button, the watchdog signal is also connected to the PF0200 PMIC_PWRON signal.  Thus configuring the PMIC in this manner breaks the ability for the watchdog to reset the board (it would need to hold the signal for 4 seconds the same as the a 4 second button press).  There is a note on the schematic for the SABRE board on the WDOG_B stating:

This block is added in Rev.C for two purposes -

i) Fix the SW reboot issue by toggling WDOG_B to issue power reset (ENGR00338067).

II) Delay the PMIC_PWRON >500ms for the 1st-time power-on (VSNVS_3V0 is first applied), to ensure 32.768kHz xtal osc output is stable.

Generally I thought the watchdog should use the POR_B instead of the PMIC_PWRON.  I looked for ENGR00338067 hoping it would have some additional details, but I could not find it.  For our custom board it would be nice to know what the real problem was and if we could find some way to work around it.  Do you have access to this note and can you share what the issue is?  I'd really appreciate it!

Thanks,

Dave

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daveebright
Contributor III

Jose,

Thanks for the information.  I'll try what you suggested by modifying the pfuze100_regulator.c file.  Do you know if once I write the registers to these values do the settings immediately take or do I have to somehow use the try-before-buy mode?  Anyway like I said I will work on this today and give an update with what I find out.

Thanks,

Dave

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