PF0100 SW1 current for i.MX6 Quad

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PF0100 SW1 current for i.MX6 Quad

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yuuki
Contributor V

Dear all,

We design a board using i.MX6Quad and PF0100.

We look at datasheets of i.MX6Qual and PF0100.
However, we think that Currents of SW1A/B and SW1C of PF0100 are not enough.

How should we understand this in designing?

In the SBRE-SD board, these are connected as follows.

- PF0100 SW1A/B [2500mA] => i.MX6Q VDDCORE(VDD_ARM_IN+VDD_ARM23_IN) [Max 3730mA]
- PF0100 SW1C [2000mA] => i.MX6Q VDDSOC(VDD_SOC_IN) [Max 2370mA]

For i.MX6Quad

imx6 max supply.png

For PF0100

PF0100 Power Tree.png

May I have advice?

Best Regards,
Yuuki

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art
NXP TechSupport
NXP TechSupport

The values of 3730mA for VDD_ARM_IN + VDD_ARM23_IN and 2370mA for VDD_SOC_IN are absolutely worst case values that are not typically achieved in real life operation. Also, as per the Table 54, sections "SW1A/B (SINGLE/DUAL PHASE)" and "SW1C (INDEPENDENT)", these regulators can provide the currents higher than 2.5A/2A for a short period of time.


Have a great day,
Artur

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koksuanliew
Contributor I

Hey Artur,

With the idea that the PMIC is able to handle some momentary high current spikes, however if the layout has not been given enough width or any poor soldering along the path where the current is needed, what will the processor experience when voltage drops (for a short moment) in those VDD_ARM and VDD_SOC pins? Is it a disgraceful black out or a temporary freeze which will come back immediately right after the current stabilized?

Regards,

Kok Suan

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art
NXP TechSupport
NXP TechSupport

The values of 3730mA for VDD_ARM_IN + VDD_ARM23_IN and 2370mA for VDD_SOC_IN are absolutely worst case values that are not typically achieved in real life operation. Also, as per the Table 54, sections "SW1A/B (SINGLE/DUAL PHASE)" and "SW1C (INDEPENDENT)", these regulators can provide the currents higher than 2.5A/2A for a short period of time.


Have a great day,
Artur

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Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

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